Senior SoC Subsystem and I/O Architect

• Define high-level SoC subsystem architecture for LPU products.
• Convert LPU product requirements into architectural specifications for uncore, IO, memory, firmware-facing, boot, reset, safety, fault tolerance, diagnostic, and power regulation subsystems.
• Build or guide functional and architectural models from specifications, using C++, SystemC, Python, or similar languages.
• Use models to validate architecture intent, subsystem behavior, configuration sequences, and IP interactions before RTL or silicon is available.
• Drive tradeoffs across bandwidth, latency, power, area, timing, scalability, reliability, security, debuggability, and software usability.
• Review IP specifications, subsystem architecture documents, model behavior, verification plans, and validation strategies.
• Collaborate with architecture, IP, firmware, software, RTL, verification, platform, and post-silicon teams to bring architecture decisions to completion.
• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
• 8+ years of proven experience in SoC architecture, subsystem architecture, IO architecture, interconnect architecture, GPU/CPU architecture, accelerator architecture, or high-performance systems.
• Strong understanding of SoC architecture and uncore subsystem development.
• Extensive understanding of IO and interconnect cores including PCIe, CXL, NVLink, NVLink-C2C, UCIe, AXI, CHI, or NoC fabrics.
• Experience working from product requirements to architecture requirements and IP/subsystem specifications.
• Experience crafting functional models, architectural models, golden models, or C/SystemC models from architecture specifications.
• Solid grasp of memory ordering, coherency, address translation, interrupts, virtualization, MMUs/IOMMUs, enumeration, configuration, and error management.
• Solid knowledge of boot, reset, firmware handoff, capability discovery, security, RAS, debug, and power-management architecture.
• Strong communication abilities and capability to harmonize architecture decisions across IP, firmware, software, verification, and product groups.
• Hands-on experience with LPU, GPU, CPU, AI accelerator, chiplet, or multi-die SoC architecture.
• Extensive knowledge in PCIe/CXL, NVLink/NVLink-C2C, UCIe, AXI/CHI, coherent fabrics, NoCs, or chip-to-chip links.
• Extensive knowledge in formulating architecture specifications for advanced SoC subsystems.
• Experience building executable functional models directly from product, architecture, or protocol specs.
• Understanding of deep learning workloads, numerics, memory architecture, and bandwidth/latency tradeoffs.
• Experience with boot architecture, reset sequencing, secure boot, RAS, debug, DFT, power sequencing, or post-silicon validation.
• You will also be eligible for equity and benefits .
• Applications for this job will be accepted at least until August 10, 2026.

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