Job description

Job Details: Job Description: The Role and Impact As a Physical Design Engineer, you will play a critical role in driving the development of cutting-edge technologies at Intel. You will work hands-on to deliver high-performance physical designs, ensuring the successful integration of advanced semiconductor technologies. Your work will directly impact Intel's product innovation, addressing complex challenges in power, performance, and area optimization to shape the future of computing architectures. From synthesis to sign-off, your contributions will enable Intel to meet ambitious design goals and deliver transformative solutions to the market. Business Group This role is part of Intel's Corporate Technology Office (CTO), a dynamic group dedicated to advancing the company's technological leadership and innovation. The group focuses on developing foundational technologies, architectures, and methodologies that drive Intel's product roadmap and enable breakthrough computing solutions. Collaborating with cross-disciplinary teams, the CTO plays a pivotal role in delivering impactful designs that support Intel's broader mission of creating world-changing technology. Key Responsibilities - Drive RTL-to-GDS design convergence using advanced synthesis and place-and-route tools targeting performance, power, and area (PPA) goals. - Deliver block-level physical design, including closure of backend flows, electrical requirements, and enhancing silicon yield. - Collaborate with CAD and physical design methodology teams to adopt industry-leading tools and optimizations for custom designs. - Execute physical implementation tasks such as floor planning, bus/pin placement, power/clock distribution, congestion analysis, timing closure, IR drop analysis, and physical verification. - Debug timing, EM/IR, LVS, and DRC violations, and drive sign-off activities for high-quality silicon production. - Work closely with custom IP teams to define and optimize memory macros and standard cell libraries to improve overall design efficiency. - Develop and refine physical design methodologies to enhance workflow and productivity. Qualifications: Minimum Qualifications - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field and 6+ years of hands-on physical design experience OR a Master's degree with 4+ years of relevant experience. - Demonstrated experience in floor planning, timing constraints definition, synthesis, place-and-route, and achieving product KPIs. - Proficiency in scripting languages such as Python, Perl, and TCL for design flow automation and debugging. - Hands-on experience with debugging functional equivalence verification (FEV) and RV reports, including planning and implementing engineering change orders (ECOs). - Strong understanding of chiplet integration and advanced packaging techniques. - Experience leveraging AI tools to set up workflows, streamline debugging, and improve productivity. Preferred Qualifications - Expertise in static timing analysis of multiple interfaces (e.g., SerDes, UCIe) and experience with industry-standard EDA tools such as Cadence Virtuoso and Synopsys Fusion Compiler. - Knowledge of asynchronous architectures and circuits and familiarity with EDA software development using object-oriented programming languages like Java or C++. - Demonstrated ability to work collaboratively across cross-functional teams, providing mentorship and guidance to junior engineers. - Experience in both power-efficient and high-frequency physical design techniques with advanced tools and methodologies. Join us in shaping the future of computing architectures. Your expertise and ideas will drive groundbreaking innovations in physical design and high-performance silicon solutions. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Requirements

Must-haves

Job Description: The Role and Impact
Business Group
Drive RTL-to-GDS design convergence using advanced synthesis and place-and-route tools targeting performance, power, and area (PPA) goals.
Deliver block-level physical design, including closure of backend flows, electrical requirements, and enhancing silicon yield.
Collaborate with CAD and physical design methodology teams to adopt industry-leading tools and optimizations for custom designs.
Execute physical implementation tasks such as floor planning, bus/pin placement, power/clock distribution, congestion analysis, timing closure, IR drop analysis, and physical verification.
Debug timing, EM/IR, LVS, and DRC violations, and drive sign-off activities for high-quality silicon production.
Work closely with custom IP teams to define and optimize memory macros and standard cell libraries to improve overall design efficiency.
Develop and refine physical design methodologies to enhance workflow and productivity.
Qualifications: Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field and 6+ years of hands-on physical design experience OR a Master's degree with 4+ years of relevant experience.
Demonstrated experience in floor planning, timing constraints definition, synthesis, place-and-route, and achieving product KPIs.
Proficiency in scripting languages such as Python, Perl, and TCL for design flow automation and debugging.
Hands-on experience with debugging functional equivalence verification (FEV) and RV reports, including planning and implementing engineering change orders (ECOs).
Strong understanding of chiplet integration and advanced packaging techniques.
Experience leveraging AI tools to set up workflows, streamline debugging, and improve productivity.

Nice-to-haves

Expertise in static timing analysis of multiple interfaces (e.g., SerDes, UCIe) and experience with industry-standard EDA tools such as Cadence Virtuoso and Synopsys Fusion Compiler.
Knowledge of asynchronous architectures and circuits and familiarity with EDA software development using object-oriented programming languages like Java or C++.
Demonstrated ability to work collaboratively across cross-functional teams, providing mentorship and guidance to junior engineers.
Experience in both power-efficient and high-frequency physical design techniques with advanced tools and methodologies.
Join us in shaping the future of computing architectures. Your expertise and ideas will drive groundbreaking innovations in physical design and high-performance silicon solutions.
Job Type: Experienced Hire
Shift: Shift 1 (United States of America)
Primary Location: US, Oregon, Hillsboro

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