Job description

APPLE INC has the following available in Austin, Texas. Work on closing the physical design, EMIR, Physical verification, and timing closure. Collaborate with the partition level or SOC level point of contact to make sure the design progresses to closure and if there are any issues while integrating design to SOC level. Use tools like Innovus, voltus and Primetime to design the partition level and interact with the edi company which develops these tools for any enhancements and bugs. Analyze the different matrices of the design like power, area, timing, and DRC to make a decision and evaluate the design for better performance. Work on developing different methodologies for better performance and faster design closure. 40 hours/week. Master’s degree or foreign equivalent in Electrical Engineering or related field and 3 years of experience in the job offered or related occupation Experience and/or education must include: Using customized scripting in Tcl, Perl, or Python to accelerate physical design closure Optimizing leakage power in post route timing tool such as Primetime Utilizing a place and route tool including Synopsys ICC or Cadence Innovus for physical design work including floorplanning and place and route implementation work. Optimizing power, timing, and area with flow adjustments to improve QoR Diagnosing timing constraint issues and provide feedback for needed exceptions Understanding localized changes to the clock tree to help close timing Diagnosing and resolving DCD (duty-cycle distortion) and MPW (min pulse-width) violations to ensure we have quality clock signals arriving to our flops and macros Utilizing static timing and noise analysis allowing resolution of violations that are not fixed by our automated tools. Utilizing a PTSI or a similar timing engine to generate ECOs to close timing N/A

Requirements

Must-haves

Master’s degree or foreign equivalent in Electrical Engineering or related field and 3 years of experience in the job offered or related occupation
Using customized scripting in Tcl, Perl, or Python to accelerate physical design closure
Optimizing leakage power in post route timing tool such as Primetime
Utilizing a place and route tool including Synopsys ICC or Cadence Innovus for physical design work including floorplanning and place and route implementation work.
Optimizing power, timing, and area with flow adjustments to improve QoR
Diagnosing timing constraint issues and provide feedback for needed exceptions
Understanding localized changes to the clock tree to help close timing
Diagnosing and resolving DCD (duty-cycle distortion) and MPW (min pulse-width) violations to ensure we have quality clock signals arriving to our flops and macros
Utilizing static timing and noise analysis allowing resolution of violations that are not fixed by our automated tools.
Utilizing a PTSI or a similar timing engine to generate ECOs to close timing

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: apple
Effort: medium