Job description

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today s innovators stay Ahead of What s Possible. Learn more at www.analog.com and on LinkedIn and X . Principal AI Accelerator Architect Lead Boston, MA; San Jose, CA Team: MicroAI Role Summary : ADI is seeking a Technology Expert in Analog and Digital AI Accelerators to define and develop a fundamentally innovative approach to artificial intelligence compute , characterized by ultra-low power consumption and deep integration within silicon. This is a practical , Hands- On , technical leadership position focused on advancing the foundational computational layers of AI, with particular emphasis on how intelligence is represented, computed, and executed within a chip under stringent power, latency, and reliability constraints. In this role, you will lead the development of system-level architecture from initial concept through to detailed design specifications. Your responsibilities will include assessing and comparing various architectural approaches, conducting in-depth evaluations of selected computing modalities, and developing system models utilizing Synopsys Platform Architect to translate insights into precise implementation specifications. Furthermore, you will collaborate closely with both internal teams and external partners across domains such as compute IP, processors, accelerators, analog and digital subsystems, firmware, and system interfaces. Key Responsibilities You will lead the effort of t ranslat ing product requirements , including functions and workloads , into end-to-end system architectures, producing well-defined specifications for IP blocks, processors, firmware, memory subsystems, and AI compute engines. Explore new representations of intelligence that go beyond conventional digital AI models and architectures Bridge the gap between academic research and real-world deployment, ensuring ideas withstand contact with physical constraints such as noise, power, variability, node scalability, and manufacturability. Lead the architecture exploration and collaborate with the modeling team to drive insights and breakthroughs Define detailed hardware block specifications and interfaces, contributing to modeling and, when appropriate, RTL development. Collaborate across architecture, design, verification, firmware, and physical design teams to ensure architectural intent is realized. Provide technical leadership and mentorship, influencing architecture decisions across multiple projects and SoC generations. Minimum Qualifications PhD or Master’s degree in Computer Engineering , Electrical Engineering, or a related technical field. 10 or more years of practical experience in digital and analog AI Accelerator systems architecture for Physical AI or embedded intelligent platforms robotics / drones / AV systems Hands-on experience with digital signal processing and both analog and digital neural-network compute architectures. Hands-On experience on how to map AI workloads and pipeline into compute requirements Experience in leadership and management roles Proven ASIC design expertise, encompassing high-speed and low-power RTL development, integrating SystemVerilog for analog compute representation, as well as familiarity with physical design flows and constraints. Strong expertise in SystemC modeling and virtual prototyping, with demonstrated ability to build and analyze complex system-level models. Deep understanding of processor architecture and design, including datapaths , memory hierarchies, interconnects, peripherals, and chip-level interfaces. Proficiency with advanced verification methodologies, including UVM, SystemVerilog , SystemC, constrained-random testing, functional coverage, and assertion-based verification. Strong programming skills in C and additional languages commonly used for modeling, simulation, or design. Excellent written and verbal communication skills. Demonstrated technical leadership, curiosity, and a strong work ethic. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law . Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days The expected wage range for a new hire into this position is $200,000 to $275,000. Actual wage offered may vary depending on work location , experience, education, training, external market data, internal pay equity, or other bona fide factors. This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time , and other benefits.

Requirements

Must-haves

Explore new representations of intelligence that go beyond conventional digital AI models and architectures
Bridge the gap between academic research and real-world deployment, ensuring ideas withstand contact with physical constraints such as noise, power, variability, node scalability, and manufacturability.
Lead the architecture exploration and collaborate with the modeling team to drive insights and breakthroughs
Define detailed hardware block specifications and interfaces, contributing to modeling and, when appropriate, RTL development.
Collaborate across architecture, design, verification, firmware, and physical design teams to ensure architectural intent is realized.
Provide technical leadership and mentorship, influencing architecture decisions across multiple projects and SoC generations.
PhD or Master’s degree in Computer Engineering , Electrical Engineering, or a related technical field.
10 or more years of practical experience in digital and analog AI Accelerator systems architecture for Physical AI or embedded intelligent platforms robotics / drones / AV systems
Hands-on experience with digital signal processing and both analog and digital neural-network compute architectures.
Hands-On experience on how to map AI workloads and pipeline into compute requirements
Experience in leadership and management roles
Proven ASIC design expertise, encompassing high-speed and low-power RTL development, integrating SystemVerilog for analog compute representation, as well as familiarity with physical design flows and constraints.
Strong expertise in SystemC modeling and virtual prototyping, with demonstrated ability to build and analyze complex system-level models.
Deep understanding of processor architecture and design, including datapaths , memory hierarchies, interconnects, peripherals, and chip-level interfaces.
Proficiency with advanced verification methodologies, including UVM, SystemVerilog , SystemC, constrained-random testing, functional coverage, and assertion-based verification.
Strong programming skills in C and additional languages commonly used for modeling, simulation, or design.
Excellent written and verbal communication skills.
Demonstrated technical leadership, curiosity, and a strong work ethic.
EEO is the Law: Notice of Applicant Rights Under the Law .
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days

Nice-to-haves

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Keywords to mirror

aigo

Platform: workday
Effort: long

Benefits

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Dental

Vision

401k