Job description

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices consumed by millions of people around the world. Come build with us! Role and Responsibilities As a Micro-Architect/Logic Designer, you will be responsible for leading the micro-architecture development of custom coherent interconnect IP and last level cache blocks. In this role you will be interacting with the system architects, verification, performance/power, and design implementation teams. You will be owning and driving the critical coherent interconnect related RTL design, performance and power optimization and also work on logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success. This role is open to being hired at various levels, based on the individual’s background, experience, and skillset. Drive the timely development of custom coherent interconnect IP and/or last level cache [LLC] blocks. Partner with architects to help define next-generation Samsung coherent interconnects and LLC. Perform microarchitecture development and specification – from early high-level architectural exploration through micro architectural research and arriving at a detailed specification Work alongside the verification team to verify the functionality and correctness of the design. Collaborate with implementation to achieve your timing and area. Produce quality RTL on schedule meeting PPA goals Engage with performance and power team on achieving performance and power goals. Work with the physical design and CAD team to resolve implementation level details. Help mentor junior engineers in the team. Skills and Qualifications 6 years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 4 years of experience with a Master’s degree, or 2 years of experience with a PhD Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs Demonstrated successful architectural through RTL design experience on high performance digital designs Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Knowledge of system caches and directory snoop filter protocols. Familiarity with different on-chip network topologies: mesh, ring, crossbar. Experience in leading and mentoring a team of engineers. Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols Knowledge of memory subsystem design including coherent cache design. Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team. Preferred candidates will possess the following: Knowledge of Verilog/VHDL, scripting, STA, DFT, ECO flows. Proficient in AMBA, ACE, AXI, CHI protocols. Knowledge of coherent interconnect, memory controller, and/or cache design. Knowledge of memory subsystem, coherency, directory snoop filter protocols. Familiarity with different on-chip network topologies: mesh, ring, crossbar. Experience with a scripting language like Perl or Python. Our Team Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem. With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments. Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture. Total Rewards At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $151,000 and $251,800. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA). Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance. Additionally, this role might be eligible to participate in long term incentive plan and relocation. Trade Secrets By submitting an application, you agree not to disclose to Samsung or induce or encourage Samsung to use any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity. U.S. Export Control This role may require access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization. #SARC #ACL * Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here . * Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

Requirements

Must-haves

Role and Responsibilities
Drive the timely development of custom coherent interconnect IP and/or last level cache [LLC] blocks.
Partner with architects to help define next-generation Samsung coherent interconnects and LLC.
Perform microarchitecture development and specification – from early high-level architectural exploration through micro architectural research and arriving at a detailed specification
Work alongside the verification team to verify the functionality and correctness of the design.
Collaborate with implementation to achieve your timing and area.
Produce quality RTL on schedule meeting PPA goals
Engage with performance and power team on achieving performance and power goals.
Work with the physical design and CAD team to resolve implementation level details.
Help mentor junior engineers in the team.
Skills and Qualifications
6 years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 4 years of experience with a Master’s degree, or 2 years of experience with a PhD
Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs
Demonstrated successful architectural through RTL design experience on high performance digital designs
Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
Knowledge of system caches and directory snoop filter protocols.
Familiarity with different on-chip network topologies: mesh, ring, crossbar.
Experience in leading and mentoring a team of engineers.
Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
Knowledge of memory subsystem design including coherent cache design.
Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.
Knowledge of Verilog/VHDL, scripting, STA, DFT, ECO flows.
Proficient in AMBA, ACE, AXI, CHI protocols.
Knowledge of coherent interconnect, memory controller, and/or cache design.

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Keywords to mirror

python

Platform: workday
Effort: long

Benefits

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Dental

Vision

401(K)

Paid Time Off

Wellness