• Definition of the PDN architecture and design solution space for systems across a wide range of power and noise specifications.
• Power delivery modeling, simulation, and characterization for die, package, module, board, and Voltage Regulator (VR)
• Definition of the PDN architecture and design solution space for the target system
• Broad responsibility on all SoC PI related topics, including on-die inrush, off-die droop budget, PDN signoffs, digital to analog/RF noise coupling analysis, voltage guard band, active droop mitigation etc.
Bachelor's degree required.
M.S. or Ph.D. with academic background in Power/Signal Integrity, Power Electronics, Electromagnetics, Microwave, and/or Analog/RF Circuit Design.
Proficiency in Python coding, AI/ML assisted automation experience.
Experience in PI/SI methodology development, PDN modeling from system to die, and lab correlation/validation.
Experience in design and analysis of product power supply solution.
Understanding of power supply architecture covering voltage regulator technologies, PCB and package design trends and trade-offs, and chip supply design including low-power design methodologies.
Deep understanding of Voltage Regulator design principles and electrical performance in the system environment.
Good knowledge in 3D/2D EM simulation tools, electromagnetic and transmission line theory.
Preferably working knowledge on analog/RF/wireless noise coupling and sensitivity
Familiar with lab equipment including but not limited to VNA, real-time scope, spectrum analyzer.
Ability to work and communicate efficiently in cross-functional teams