Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. SerDes IP Systems Engineering Director Description:     This is a unique opportunity to join the rapidly growing Die-to-Die Interface IP team in the Silicon Solutions R&D Group at Cadence Design Systems. We are looking for a Systems Engineering Director who will be a key driver and contributor to the development of our advanced D2D SerDes IP products. This role involves leading the D2D Systems analysis team as well as contributing with hands on technical development.  Main Job Tasks and Responsibilities: Key contributor and driver of the R&D team that defines, models and analyzes high performance D2D SerDes IP microarchitecture, link budget and specifications Develop infrastructure to ensure robust product development, systems modeling analysis and testing Develop statistical and linear systems analysis of the link, model nonidealities and determine design specifications for circuit designers Drive and verify end-to-end link simulations using statistical and time-domain simulators (Simulink, ADS, etc.) Develop and provide guidelines regarding signal integrity and power integrity to customers Support customer package/board design and debug as necessary Guide the package design team based on in-package D2D link channel analysis Generate technical specification, data sheets, and application notes Update R&D team with the latest standards developments, customer feedback and competitive analysis              Position Requirements:               Must have strong group presentation and leadership skills PhD or M.S. in Electrical/Computer Engineering (or similar degree) 10 years of experience working with high speed high performance SerDes and PHYs The ability to think through engineering systems end-to-end and identify bottlenecks and weak points. Strong mathematical skills, in particular relating to linear systems (Fourier analysis, filter theory, etc.) Deep understanding of high speed SerDes architecture Proficient in MATLAB, Simulink, ADS, or similar link analysis/statistical analysis tool Deep knowledge of communication systems fundamentals and wireline communications Strong coding skills for simulation and modelling, as well as data analysis Good experimental skills Good knowledge of signal processing (DSP) algorithms and architecture. Good working knowledge of physics of signal propagation Good working knowledge of basic circuits Experience generating systems or IBIS-AMI models Experience using system simulation tools, especially Matlab, Perl, and other scripting tools Demonstrated capacity to self-educate themselves to pick up new fields of expertise D2D link experience is preferred but not required Familiarity with emerging D2D standards such as UCIe is desired Strong debug and problem-solving skills The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.

Requirements

Must-haves

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. SerDes IP Systems Engineering Director Description:
Key contributor and driver of the R&D team that defines, models and analyzes high performance D2D SerDes IP microarchitecture, link budget and specifications
Develop infrastructure to ensure robust product development, systems modeling analysis and testing
Develop statistical and linear systems analysis of the link, model nonidealities and determine design specifications for circuit designers
Drive and verify end-to-end link simulations using statistical and time-domain simulators (Simulink, ADS, etc.)
Develop and provide guidelines regarding signal integrity and power integrity to customers
Support customer package/board design and debug as necessary
Guide the package design team based on in-package D2D link channel analysis
Generate technical specification, data sheets, and application notes
Update R&D team with the latest standards developments, customer feedback and competitive analysis
Must have strong group presentation and leadership skills
PhD or M.S. in Electrical/Computer Engineering (or similar degree)
10 years of experience working with high speed high performance SerDes and PHYs
The ability to think through engineering systems end-to-end and identify bottlenecks and weak points.
Strong mathematical skills, in particular relating to linear systems (Fourier analysis, filter theory, etc.)
Deep understanding of high speed SerDes architecture
Proficient in MATLAB, Simulink, ADS, or similar link analysis/statistical analysis tool
Deep knowledge of communication systems fundamentals and wireline communications
Strong coding skills for simulation and modelling, as well as data analysis
Good experimental skills
Good knowledge of signal processing (DSP) algorithms and architecture.
Good working knowledge of physics of signal propagation
Good working knowledge of basic circuits

Nice-to-haves

D2D link experience is preferred but not required

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

design systems

Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)