Job description

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! Join our silicon design verification team and work closely with digital/analog designers, applications engineers, and manufacturing test, participating in all aspects of verification for complete mixed-signal IC developments of innovative solutions. You will work on complex verification systems and contribute to improvements in verification methodology while working alongside some of the most talented engineers in our industry. Responsibilities: Perform verification planning. Testbench development using UVM methodologies. Implement functional verification of mixed-signal ASICs. Failure analysis and resolution, coverage analysis and population. Digital/mixed-signal modeling. Develop directed/constraint-random test generation, gate-simulations. Regression debug support and other flow/infrastructure development. Required Skills and Qualifications: MS or PhD in Electrical Engineering or Computer Engineering. Strong background with HDLs (e.g. Verilog, VHDL) and HVLs (e.g. SystemVerilog/UVM, OVM, AVM, Vera). At least 5+ years of experience in silicon design or verification. Preferred Skills and Qualifications: Able to work closely with digital/analog designers, applications engineers, and manufacturing test to support both pre-silicon verification and post-silicon validation efforts. Knowledge of signal processing and Verilog Assertions. Ability to create, evaluate, debug, and improve verification processes. Ability to mentor junior engineers in verification methodology. #LI-Hybrid #LI-EK1 Export control restrictions based upon applicable laws and regulations would prohibit candidates who are nationals of certain embargoed countries from working in this position without Cirrus Logic first obtaining an export license. Candidates for this role must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role. Cirrus Logic strives to select the best qualified applicant for any opening. Different approaches, ideas and points of view are both valued and respected. Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.

Requirements

Must-haves

Perform verification planning.
Testbench development using UVM methodologies.
Implement functional verification of mixed-signal ASICs.
Failure analysis and resolution, coverage analysis and population.
Digital/mixed-signal modeling.
Develop directed/constraint-random test generation, gate-simulations.
Regression debug support and other flow/infrastructure development.
MS or PhD in Electrical Engineering or Computer Engineering.
Strong background with HDLs (e.g. Verilog, VHDL) and HVLs (e.g. SystemVerilog/UVM, OVM, AVM, Vera).
At least 5+ years of experience in silicon design or verification.
Able to work closely with digital/analog designers, applications engineers, and manufacturing test to support both pre-silicon verification and post-silicon validation efforts.
Knowledge of signal processing and Verilog Assertions.
Ability to create, evaluate, debug, and improve verification processes.
Ability to mentor junior engineers in verification methodology.

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: lever
Effort: quick