Job description

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Job Overview: Qualcomm’s SoC Platform Architecture team defines platform architectures & solutions enabling the next-generation of system-on-chip (SoC) products across Qualcomm’s business lines including compute, automotive, mobile, wearables, XR and IoT with focus in utilizing RISC-V architecture. Our team performs analysis, defines, and delivers innovative and scalable architectures across key technologies including heterogenous compute, memory systems, interconnects, multimedia, AI/ML, multi-die, power-management and more. We collaborate directly with software, systems, design, product marketing, and customers. We are currently seeking SoC Architect with proven expertise in defining and delivering RISC-V Application Processor SoCs, including key platform technologies such as AIA, IOMMU, CBQRI, debug & security architecture etc to join us in our mission to innovate and deliver the most advanced and scalable SoC platform architectures in the industry. Responsibilities includes but not limited to: • Create highly scalable SoC architecture using RISC-V architecture. • Have knowledge in the area of SoC control, boot, reset, timebase management, debug, micro-controllers, etc. • Comprehend product requirements to steer generation of proper architecture. • Perform trade-off analysis in the solution space to produce the most optimal architecture. • Collaborate with architects, technical leads, hardware and software engineers from various functional areas in deriving the architectural solution that can best integrate in the overall SoC. • Generate detail architectural specification and work closely with design team to implement the architecture. Skills/Experience : • Experienced in RISC-V AP platform architecture particularly in the area of AIA, CBQRI, IOMMU, debug security, etc. • Excellent communication, documentation, and interpersonal skills with ability to convey proposals and interact effectively across a distributed multi-discipline organization • Strong foundation of silicon design principles and architectural trade-offs • Ability to span and connect levels of abstraction across system-design, high-level languages, OS, HW/SW interface, micro-architecture, and silicon implementation • Background in architecture (IP or SoC), and/or front-end design/verification (micro-architecture) • Demonstrated deep technical knowledge and achievements at the SoC, sub-system or large IP levels as micro-architect or architect • Ability to apply appropriate abstractions and quantitative analysis for problem definition and solutions • Experience in using, improving, and developing a variety of tools for analysis and modeling, such as functional and performance simulators, profilers, etc. • Programming ability for modeling and automation (OOP C++, Python preferred) with experience in software development best practices including reviews, unit-testing, version control, etc. • Ability and desire to develop and improve architecture methodologies for experiments and analysis • Preferred with experience in the SoC areas such as boot, timebase management and network, security architecture, reset architecture and debug architecture, system level control/management with components such as BMC, ECU, etc. Minimum Qualifications: • Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. Preferred Minimum Qualifications: • Bachelor’s degree in Electronic Engineering, Computer Science or related field required; Master’s degree or PhD highly desired • 5+ years of SoC/IP architecture or micro-architecture/front-end-design • Candidates with primarily a micro-architecture/design background must have contributions that demonstrate higher-level analysis and design Additional Experience and Expertise (the more the better) • SoC architectures including heterogeneous compute, NoC/interconnect, memory-systems, multicore, multi-die, cache hierarchies, shared memory, I/O, coherency, compression, security • Resource and Power Management • Security Architecture • System-level debug • Safety, reliability, and high-resilience/high-availability systems • AI & Machine Learning • Control and Real-time systems • High-level Operating Systems (e.g., Android, Linux, Windows) • Real-time operating systems (e.g., Zephyr, FreeRTOS) • Front-end Digital Hardware Design or Verification • Arm system architectures (e.g., Cortex-A, Cortex-R, Cortex-M, CoreSight) • High-speed I/O (USB, PCIe, CXL) • External memory and storage architectures (e.g., LPDDR, NAND Flash, NOR Flash) • Networking & Connectivity (e.g., Ethernet, WLAN, Cellular, CAN) • Behavioral, functional and performance modeling • Power and/or performance optimization through simulation & modeling • Simulator architectures and frameworks (C++ or Python-based preferred) • Analytical modeling for performance and power Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits : $174,400.00 - $261,600.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link . If you would like more information about this role, please contact Qualcomm Careers .

Requirements

Must-haves

Qualcomm Technologies, Inc.
Engineering Group, Engineering Group > ASICS Engineering
Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Create highly scalable SoC architecture using RISC-V architecture.
Have knowledge in the area of SoC control, boot, reset, timebase management, debug, micro-controllers, etc.
Comprehend product requirements to steer generation of proper architecture.
Perform trade-off analysis in the solution space to produce the most optimal architecture.
Collaborate with architects, technical leads, hardware and software engineers from various functional areas in deriving the architectural solution that can best integrate in the overall SoC.
Generate detail architectural specification and work closely with design team to implement the architecture.
Experienced in RISC-V AP platform architecture particularly in the area of AIA, CBQRI, IOMMU, debug security, etc.
Excellent communication, documentation, and interpersonal skills with ability to convey proposals and interact effectively across a distributed multi-discipline organization
Strong foundation of silicon design principles and architectural trade-offs
Ability to span and connect levels of abstraction across system-design, high-level languages, OS, HW/SW interface, micro-architecture, and silicon implementation
Background in architecture (IP or SoC), and/or front-end design/verification (micro-architecture)
Demonstrated deep technical knowledge and achievements at the SoC, sub-system or large IP levels as micro-architect or architect
Ability to apply appropriate abstractions and quantitative analysis for problem definition and solutions
Experience in using, improving, and developing a variety of tools for analysis and modeling, such as functional and performance simulators, profilers, etc.
Ability and desire to develop and improve architecture methodologies for experiments and analysis
Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.
Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.

Nice-to-haves

Programming ability for modeling and automation (OOP C++, Python preferred) with experience in software development best practices including reviews, unit-testing, version control, etc.
Simulator architectures and frameworks (C++ or Python-based preferred)

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aimlpythonmachine learningrest

Platform: eightfold
Effort: medium