Job description

Imagine yourself at the center of our SOC design effort, collaborating with all disciplines, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of talented engineers. As a Circuit Design Engineering Lead for the custom circuits team, you will perform the following: - Drive development of high performance, low power optimized standard cells to improve design PPA. - Drive development of optimal level shifters, retention designs, etc that cater to today’s Low Power Design Requirements. - Identify next generation of new ideas to drive PPA improvements further - Engage with CPU, SOC and GPU teams on chip level integration requirements. - Drive Circuit QA checks & analysis, develop new methodologies based on new design requirements. - Work with foundries on DRM complaint layout checkers and iPDK requirements. - Plan & drive development of designs like new circuits & tech node enablement. - Manage migration to new PDK, PDV of standard cells & releases. Bachelor's Degree + minimum of 3 years of experience We are looking for applicants with 3+ years of experience in Standard cells circuit development. Proven experience in developing, driving & implementing circuit methodologies Proven experience leading & mentoring a small team Strong influence, excellent interpersonal skills & able to work with multi-functional teams Knowledge of standard cell layout, DRM, DRC/LVS decks, PDV flows, Virtuoso. Design experience in advanced tech node device behavior with understanding of layout rules. Design experience in flop, complex Standard Cells design & Power Management Cells.  Knowledge of circuit robustness analysis  Experience in scripting in Perl and/or TCL.

Requirements

Must-haves

Drive development of high performance, low power optimized standard cells to improve design PPA.
Drive development of optimal level shifters, retention designs, etc that cater to today’s Low Power Design Requirements.
Identify next generation of new ideas to drive PPA improvements further
Engage with CPU, SOC and GPU teams on chip level integration requirements.
Drive Circuit QA checks & analysis, develop new methodologies based on new design requirements.
Work with foundries on DRM complaint layout checkers and iPDK requirements.
Plan & drive development of designs like new circuits & tech node enablement.
Manage migration to new PDK, PDV of standard cells & releases.
Bachelor's Degree + minimum of 3 years of experience
We are looking for applicants with 3+ years of experience in Standard cells circuit development.
Proven experience in developing, driving & implementing circuit methodologies
Proven experience leading & mentoring a small team
Strong influence, excellent interpersonal skills & able to work with multi-functional teams
Knowledge of standard cell layout, DRM, DRC/LVS decks, PDV flows, Virtuoso.
Design experience in advanced tech node device behavior with understanding of layout rules.
Design experience in flop, complex Standard Cells design & Power Management Cells.
 Knowledge of circuit robustness analysis
 Experience in scripting in Perl and/or TCL.

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: apple
Effort: medium