Job description

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value. About the team We're the team behind post-silicon bring-up, debug, and validation for the high-speed IO and memory subsystems in SambaNova's DataScale platform. We own the path from first silicon power-on through field deployment: characterization, stress testing, performance validation, and root-causing issues across silicon, board, and software. We work directly with design, firmware, verification, and system engineering to keep bring-up on schedule, and partner with customer engineering on deployment and RMA debug. We build our own debug tooling and automation, and apply what we learn to pre-silicon verification to improve coverage on future programs. About the role div]:bg-bg-000/50 [&_pre>div]:border-0.5 [&_pre>div]:border-border-400 [&_.ignore-pre-bg>div]:bg-transparent [&_.standard-markdown_:is(p,blockquote,h1,h2,h3,h4,h5,h6)]:pl-[var(--msg-text-inset,0.5rem)] [&_.standard-markdown_:is(p,blockquote,ul,ol,h1,h2,h3,h4,h5,h6)]:pr-8 [&_.progressive-markdown_:is(p,blockquote,h1,h2,h3,h4,h5,h6)]:pl-[var(--msg-text-inset,0.5rem)] [&_.progressive-markdown_:is(p,blockquote,ul,ol,h1,h2,h3,h4,h5,h6)]:pr-8"> _*]:min-w-0 gap-3 [&_>_*:last-child]:mb-0 print:block print:[&_>_:where(:not(:first-child))]:mt-3 standard-markdown"> SambaNova is seeking a Principal Engineer to own post-silicon bring-up, debug, and validation of high-speed IO and memory subsystems within the DataScale® platform. This role is central to delivering reliable, high-performance AI systems at scale. You'll lead system-level debug across silicon, board, and software layers, driving issues to root cause from first silicon through field deployment. This is a hands-on role for an engineer with deep expertise in high-speed interfaces and hardware debug, who can operate in ambiguity and execute with high ownership. Responsibilities Own post-silicon bring-up and validation of high-speed IO and memory subsystems, spanning characterization, functional validation, stress testing, and performance analysis Establish power-on readiness ahead of first silicon, including debug infrastructure, tooling, and contingency planning Lead system-level debug to root cause complex issues spanning silicon, board, and software layers Drive resolution with design, firmware, verification, and system teams to close issues and keep bring-up on schedule Partner with system and customer engineering teams on product validation, deployment, and RMA debug Own validation sign-off for product release against stability, performance, and field reliability targets Review SoC and board design and SI/PI analysis through a post-silicon debug and deployment lens Contribute to pre-silicon verification and emulation to improve bring-up efficiency and coverage Build scripts and tooling that automate validation, debug, and data analysis, and scale test coverage across systems Advance post-silicon validation methodology and debug infrastructure across programs Required qualifications M.S. in Electrical Engineering, Computer Science, or a related field 7+ years of experience in post-silicon validation or system bring-up Experience with two or more high-speed IO or memory protocols such as PCIe, Ethernet, HBM, CXL, or UCIe Proven ability to lead cross-functional debug efforts to root cause and closure Strong analytical skills for test development and data analysis Proficiency in scripting such as Python and bash Clear and effective communicator with a proactive, collaborative approach to problem-solving Preferred qualifications Deep understanding of high-speed SerDes training and adaptation Experience with mixed-signal IO design and validation Hands-on lab experience with oscilloscopes, protocol analyzers, and BERTs Experience with optical interconnect Ability to read and debug C/C++ Base Salary Range: Base Pay Range $180,000 — $255,000 USD Submission Guidelines Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified. EEO Policy SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws. Benefits Summary for US-Based, Full-Time Employment Positions SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.

Requirements

Must-haves

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Own post-silicon bring-up and validation of high-speed IO and memory subsystems, spanning characterization, functional validation, stress testing, and performance analysis
Establish power-on readiness ahead of first silicon, including debug infrastructure, tooling, and contingency planning
Lead system-level debug to root cause complex issues spanning silicon, board, and software layers
Drive resolution with design, firmware, verification, and system teams to close issues and keep bring-up on schedule
Partner with system and customer engineering teams on product validation, deployment, and RMA debug
Own validation sign-off for product release against stability, performance, and field reliability targets
Review SoC and board design and SI/PI analysis through a post-silicon debug and deployment lens
Contribute to pre-silicon verification and emulation to improve bring-up efficiency and coverage
Build scripts and tooling that automate validation, debug, and data analysis, and scale test coverage across systems
Advance post-silicon validation methodology and debug infrastructure across programs
M.S. in Electrical Engineering, Computer Science, or a related field
7+ years of experience in post-silicon validation or system bring-up
Experience with two or more high-speed IO or memory protocols such as PCIe, Ethernet, HBM, CXL, or UCIe
Proven ability to lead cross-functional debug efforts to root cause and closure
Strong analytical skills for test development and data analysis
Proficiency in scripting such as Python and bash
Clear and effective communicator with a proactive, collaborative approach to problem-solving

Nice-to-haves

Deep understanding of high-speed SerDes training and adaptation
Experience with mixed-signal IO design and validation
Hands-on lab experience with oscilloscopes, protocol analyzers, and BERTs
Experience with optical interconnect
Ability to read and debug C/C++

Application prep

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Keywords to mirror

aipython

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Benefits

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Dental

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