Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for a skilled engineer to join our Power Analysis team, focused on developing, debugging, and deploying Signoff power analysis flows at customer environments. Key Responsibilities Closely work with R&D to develop and maintain Signoff power analysis flows including integration with synthesis and PnR stages Reproduce, debug, and resolve customer-reported issues in power analysis tools and flows Deploy and validate power analysis tools at customer sites; provide hands-on technical support Collaborate with customers to optimize power results and improve flow efficiency Contribute to flow automation and scripting for repeatable deployments Document debug findings, best practices, and flow guidelines Required Skills Hands-on experience with Signoff power analysis (static and dynamic power) Knowledge of power optimization techniques in Synthesis (clock gating, operand isolation, multi-Vt cell selection, Working knowledge of UPF (Unified Power Format) — power domains, isolation, level shifting, retention Proficiency in Verilog/SystemVerilog for design analysis and testcase creation Understanding of digital design fundamentals — clock domains, pipeline stages, timing/power trade-offs Experience with low-power design methodologies (DVFS, power gating, multi-voltage) Familiarity with Liberty (.lib) and SPEF formats Scripting skills: Tcl, Python, or Shell Familiarity with tools such as Joules, Voltus, PTPX or equivalent Education & Experience B.E./B.Tech or M.E./M.Tech in Electronics / VLSI / Computer Engineering or equivalent Must have 3 years of industry work experience The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.

Requirements

Must-haves

Key Responsibilities Closely work with R&D to develop and maintain Signoff power analysis flows including integration with synthesis and PnR stages
Reproduce, debug, and resolve customer-reported issues in power analysis tools and flows
Deploy and validate power analysis tools at customer sites; provide hands-on technical support
Collaborate with customers to optimize power results and improve flow efficiency
Contribute to flow automation and scripting for repeatable deployments
Document debug findings, best practices, and flow guidelines
Required Skills Hands-on experience with Signoff power analysis (static and dynamic power)
Knowledge of power optimization techniques in Synthesis (clock gating, operand isolation, multi-Vt cell selection,
Working knowledge of UPF (Unified Power Format) — power domains, isolation, level shifting, retention
Proficiency in Verilog/SystemVerilog for design analysis and testcase creation
Understanding of digital design fundamentals — clock domains, pipeline stages, timing/power trade-offs
Experience with low-power design methodologies (DVFS, power gating, multi-voltage)
Familiarity with Liberty (.lib) and SPEF formats
Scripting skills: Tcl, Python, or Shell
Familiarity with tools such as Joules, Voltus, PTPX or equivalent
Education & Experience B.E./B.Tech or M.E./M.Tech in Electronics / VLSI / Computer Engineering or equivalent
Must have 3 years of industry work experience
We’re doing work that matters. Help us solve what others can’t.

Nice-to-haves

None flagged.

Application prep

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Keywords to mirror

python

Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)