Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This is an opportunity to join a dynamic team of experienced engineers developing physical IP for industry-standard high-speed serial-links. The successful candidate will ideally be a highly-motivated self-starter who can work independently to complete assigned tasks and contribute to project leadership. The candidate will contribute to all mixed-signal design, verification, and testing aspects. This includes circuit design and development from a high-level architectural specification, post-silicon test plan development and execution, and collaboration with the digital team to achieve functional and performance closure. Candidate must have a thorough understanding of the following: Mixed-signal circuit design fundamentals Mixed-signal circuit design and verification flows Cadence analog design environment Basic signal processing concepts Familiarity with the following items is a plus: Serial link design techniques Data converter (ADCs and/or DACs) and/or clock synthesis and recovery (PLLs, DLLs, CDRs) techniques MATLAB or C to facilitate architecture development Hardware description languages such as SystemVerilog or VerilogA for functional model development Scripting languages such as Perl or Python for automation Silicon validation testing knowledge and experience Other requirements: Excellent verbal and written communication skills Ph.D. EE degree with 5 years or MS EE. degree with 7 years of mixed signal design industry experience in advanced process technologies The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.

Requirements

Must-haves

Candidate must have a thorough understanding of the following:
Mixed-signal circuit design fundamentals
Mixed-signal circuit design and verification flows
Cadence analog design environment
Basic signal processing concepts
Serial link design techniques
Data converter (ADCs and/or DACs) and/or clock synthesis and recovery (PLLs, DLLs, CDRs) techniques
MATLAB or C to facilitate architecture development
Hardware description languages such as SystemVerilog or VerilogA for functional model development
Scripting languages such as Perl or Python for automation
Silicon validation testing knowledge and experience
Excellent verbal and written communication skills
Ph.D. EE degree with 5 years or MS EE. degree with 7 years of mixed signal design industry experience in advanced process technologies
We’re doing work that matters. Help us solve what others can’t.

Nice-to-haves

Familiarity with the following items is a plus:

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)