Job description

• As a member of our physical design team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level. • You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout. • You will lead schedules and support cross-functional engineering efforts. • You will work on padring, bump, RDL design, and working with the package and floorplan teams. BS and 10+ years of relevant industry experience. Experienced with physical verification flows such as DRC/LVS/ANT/HVDRC signoff flows and full-chip integration methodology Experience with ESD and macro placement design guidelines, digital and analog mixed signal back-end verification checks and methodology Knowledge of all aspects of ASIC physical design and physical verification checks for hierarchical designs including full-chip flows Scripting skills perl/python/tcl to debug flow related issues and automate checks Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc. Tapeout experience with a track record of successful signoffs Layout design experience is a plus

Requirements

Must-haves

As a member of our physical design team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level.
You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.
You will lead schedules and support cross-functional engineering efforts.
You will work on padring, bump, RDL design, and working with the package and floorplan teams.
BS and 10+ years of relevant industry experience.
Experienced with physical verification flows such as DRC/LVS/ANT/HVDRC signoff flows and full-chip integration methodology
Experience with ESD and macro placement design guidelines, digital and analog mixed signal back-end verification checks and methodology
Knowledge of all aspects of ASIC physical design and physical verification checks for hierarchical designs including full-chip flows
Scripting skills perl/python/tcl to debug flow related issues and automate checks
Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.
Tapeout experience with a track record of successful signoffs

Nice-to-haves

Layout design experience is a plus

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: apple
Effort: medium