Job description

ASIC Design Manager Location: Louisville, CO or Beaverton, OR Organization: ASIC Development Group, Tektronix Overview At Tektronix, we believe innovation starts with our customers. For more than eighty years, we have delivered industry-leading test and measurement solutions that help engineers solve complex challenges around the world. Our engineering culture is collaborative, technically rigorous, and committed to innovation, continuous learning, and professional growth. We are seeking an ASIC Design Manager to lead and grow our digital ASIC design and realization organization. ASICs are at the core of Tektronix’s next-generation instrumentation platforms, and this role is responsible for execution across the complete ASIC flow, from architecture and RTL development through IP integration, physical design, signoff, tapeout, and silicon bring-up. This hands-on leadership role combines people management, vendor relations, technical direction, and project execution. You will lead engineers responsible for digital design, verification, and physical implementation while remaining engaged in critical architecture, implementation, timing closure, power integrity, and signoff decisions. The successful candidate will bring strong experience in ASIC development and the ability to guide a multidisciplinary team through complex technical and program challenges. Key Responsibilities • Lead, mentor, and develop a team of digital ASIC design, verification, and physical design engineers; establish clear priorities, support career growth, and foster a collaborative engineering culture. • Own the end-to-end digital ASIC development flow, including microarchitecture, RTL development, IP selection and integration, synthesis, constraints development, floorplanning, clock-tree synthesis, place-and-route, timing closure, and tapeout. • Set technical direction for digital IP, subsystem design, full-chip integration, and physical implementation, balancing performance, power, area, reliability, reuse, cost, and schedule. • Drive physical design planning and execution, including floorplanning, power-grid architecture, clock distribution, congestion analysis, routing optimization, engineering change orders, and design closure. • Have knowledge of digital-on-top development flows for mixed-signal designs. • Oversee signoff activities, including static timing analysis, signal integrity, power integrity, IR-drop analysis, electromigration analysis, formal equivalence, DRC, LVS, and tapeout-readiness reviews. • Partner with product and system architects to translate product requirements into ASIC specifications, partitioning strategies, interfaces, and performance targets. • Coordinate execution across functional UVM verification, DFT, CAD, packaging, validation, product engineering, foundry, and external design-services teams. • Collaborate with package design and process-technology teams on die planning, bump assignments, power delivery, thermal performance, manufacturability, and package integration. • Develop and execute project plans with program management, including schedules, resource plans, cost estimates, milestone tracking, and risk mitigation. • Drive design quality through disciplined methodologies, technical reviews, lint and CDC readiness, implementation checks, and signoff criteria. • Improve design flows, automation, and engineering practices to increase productivity, quality, reuse, and schedule predictability. • Support silicon bring-up, characterization, post-silicon debug, and production-readiness activities. • Recruit and retain engineering talent, and manage contractors, external design-service providers, IP vendors, and other technical partners as needed. • Contribute directly to technical reviews and critical design or implementation work when it helps accelerate the team or reduce project risk. A Typical Day Might Include • Reviewing a microarchitecture proposal or RTL implementation and helping resolve an interface, performance, or integration issue. • Leading a floorplan or implementation review and evaluating tradeoffs among timing, power, congestion, area, and reliability. • Working with physical design engineers to resolve timing, IR-drop, electromigration, signal-integrity, or physical-verification issues before tapeout. • Collaborating with architects, packaging engineers, and foundry partners to refine system partitioning and die-to-package integration. • Meeting with IP and design services vendors to discuss possible engagements. • Reviewing project status with program management, addressing technical risks, and adjusting priorities or resources. • Coaching an engineer, conducting a technical review, or interviewing a candidate. Minimum Qualifications • Bachelor’s degree in Electrical Engineering, Computer Engineering, a related technical discipline, or equivalent practical experience. • Significant experience developing ASICs or complex digital integrated circuits, including digital design and physical implementation activities. • Experience leading technical projects, mentoring engineers, or coordinating work across multidisciplinary engineering teams. • Strong understanding of digital design methodologies, including microarchitecture, synthesizable SystemVerilog or Verilog RTL, IP integration, synthesis, constraints development, and static timing analysis. • Experience with physical design and implementation, including several of the following: floor-planning, power planning, clock-tree synthesis, place-and-route, timing closure, engineering change orders, power integrity, or physical signoff. • Familiarity with ASIC verification, DFT, packaging, CAD, and silicon validation interfaces and handoffs. • Experience using industry-standard ASIC design, implementation, timing, or signoff tools from Cadence, Synopsys, Siemens EDA, or equivalent providers. • Experience supporting an ASIC through major development milestones such as design closure, tapeout, silicon bring-up, qualification, or production release. • Strong communication, collaboration, organizational, and problem-solving skills, with the ability to work effectively across engineering, product, and program-management teams. Preferred Qualifications • Experience managing or formally leading engineering teams, including hiring, coaching, career development, and resource planning. • Master’s or doctoral degree in Electrical Engineering, Computer Engineering, or a related field. • Experience leading end-to-end digital ASIC or SoC implementation through tapeout. • Experience with high-speed digital or mixed-signal ASICs, DSP architectures, data-converter interfaces, or instrumentation applications. • Experience with multi-mode, multi-corner timing analysis; signal-integrity analysis; IR-drop and electromigration verification; or other physical signoff methodologies. • Experience optimizing designs for performance, power, area, yield, reliability, and manufacturability. • Familiarity with flip-chip packaging, bump planning, package co-design, multi-chip modules, chiplets, or other advanced packaging technologies. • Experience with FPGA prototyping, emulation, or other pre-silicon validation methods. • Experience collaborating with foundries, OSAT partners, external IP vendors, EDA suppliers, or design-services providers. • Experience improving ASIC development methodologies, automation, and team execution practices. Why Join Tektronix? This role offers the opportunity to shape the future of Tektronix instrumentation platforms while leading a talented engineering team responsible for strategic silicon development. You will influence technology direction, engineering methodology, and program execution while helping deliver ASIC solutions that enable the next generation of test and measurement innovation. #LI-RG1

Requirements

Must-haves

ASIC Design Manager
Location: Louisville, CO or Beaverton, OR
Organization: ASIC Development Group, Tektronix
Lead, mentor, and develop a team of digital ASIC design, verification, and physical design engineers; establish clear priorities, support career growth, and foster a collaborative engineering culture.
Set technical direction for digital IP, subsystem design, full-chip integration, and physical implementation, balancing performance, power, area, reliability, reuse, cost, and schedule.
Drive physical design planning and execution, including floorplanning, power-grid architecture, clock distribution, congestion analysis, routing optimization, engineering change orders, and design closure.
Have knowledge of digital-on-top development flows for mixed-signal designs.
Oversee signoff activities, including static timing analysis, signal integrity, power integrity, IR-drop analysis, electromigration analysis, formal equivalence, DRC, LVS, and tapeout-readiness reviews.
Partner with product and system architects to translate product requirements into ASIC specifications, partitioning strategies, interfaces, and performance targets.
Coordinate execution across functional UVM verification, DFT, CAD, packaging, validation, product engineering, foundry, and external design-services teams.
Collaborate with package design and process-technology teams on die planning, bump assignments, power delivery, thermal performance, manufacturability, and package integration.
Develop and execute project plans with program management, including schedules, resource plans, cost estimates, milestone tracking, and risk mitigation.
Drive design quality through disciplined methodologies, technical reviews, lint and CDC readiness, implementation checks, and signoff criteria.

Nice-to-haves

Experience managing or formally leading engineering teams, including hiring, coaching, career development, and resource planning.
Master’s or doctoral degree in Electrical Engineering, Computer Engineering, or a related field.
Experience leading end-to-end digital ASIC or SoC implementation through tapeout.
Experience with high-speed digital or mixed-signal ASICs, DSP architectures, data-converter interfaces, or instrumentation applications.
Experience with multi-mode, multi-corner timing analysis; signal-integrity analysis; IR-drop and electromigration verification; or other physical signoff methodologies.
Experience optimizing designs for performance, power, area, yield, reliability, and manufacturability.
Familiarity with flip-chip packaging, bump planning, package co-design, multi-chip modules, chiplets, or other advanced packaging technologies.
Experience with FPGA prototyping, emulation, or other pre-silicon validation methods.
Experience collaborating with foundries, OSAT partners, external IP vendors, EDA suppliers, or design-services providers.
Experience improving ASIC development methodologies, automation, and team execution practices.
Why Join Tektronix?

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: oracle-cloud
Effort: medium