Job description

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities. The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing! Location: Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy. What You’ll Do Develop RTL (Verilog/SystemVerilog) for the IO die, integrating UCIe, PCIe, and other high-speed interconnect IP into a cohesive chiplet-based architecture. Integrate internal and third-party interconnect IP — UCIe, PCIe, CXL, die-to-die, and NoC — into the IO die, including configuration, glue logic, clock/reset, and interface bridging. Modify and customize PCIe and other interconnect IP as needed — controller, PIPE/PHY interface, and configuration logic — to meet die-level requirements and close functional gaps. Define and implement die-to-die and chiplet interfaces using UCIe, ensuring protocol compliance and interoperability across chiplets. Own the microarchitecture and RTL for IO subsystems such as PCIe/CXL controllers, UCIe adapters, and interconnect fabric bridges. Collaborate with verification engineers to develop test plans and debug functional issues at the IP, subsystem, and die level. Work with architecture, PHY/SerDes, physical design, and software teams to close requirements across performance, power, area, and interoperability. Make design decisions out of a large design trade-off space across performance, power, latency, bandwidth, and cost. Develop and automate IP integration and RTL assembly flows using scripting and agentic AI tools and frameworks to improve turnaround time and quality of results. Communicate effectively with stakeholders, including users, partners, and management, to ensure that the die is delivered on time and within budget. Complete other responsibilities as assigned. What You Bring Bachelor’s with 5+ years, or Master’s with 3+ years, or PhD's with 0+ years of industry experience. Strong background in microarchitecture and RTL design for complex SoC and die integration. 5+ years of experience in RTL development (Verilog/SystemVerilog) for high-speed interconnect and IO subsystems. Hands-on experience integrating and configuring interconnect IP such as PCIe, CXL, UCIe, and die-to-die interfaces. Experience modifying or customizing third-party interconnect IP (e.g., PCIe controller, PIPE, or PHY interface) to meet die-level requirements. Familiarity with UCIe and chiplet-based, multi-die architectures and die-to-die interconnect. Solid understanding of PCIe/CXL protocol stacks (transaction, data link, and physical layers) and the PIPE interface. Experience with SoC integration methodologies, IP packaging (e.g., IP-XACT), and on-chip interface protocols such as AXI, ACE, CHI, or APB. Proficiency in scripting (Tcl, Python, or Perl) for design integration and automation; familiarity with agentic AI tools and frameworks is a plus. Experience in AI/ML workloads. Strong analytical and problem-solving skills Excellent communication and interpersonal skills Ability to work independently and as part of a team You’re inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change #LI-VL1 What We Offer The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community. Enjoy Time Away You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge. Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, caregiver support, and medical travel support. Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you’ll have support no matter where you are. Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier. Embrace Flexibility Benefits are best when you have the space to use them. That’s why we facilitate a flexible environment so you can find the right balance for you. Base Pay Range $138,000 — $206,000 USD Equal Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Our Commitment to Innovation and Fairness At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency. However, AI is used as a support tool, not a final decision-maker. All hiring decisions are made by our human recruiting team and hiring managers to ensure every candidate is evaluated fairly and holistically. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we ask that candidates rely on their own knowledge and skills throughout the process. AI tools may be used for basic preparation, grammar, and research, but should not be used to generate or assist with submitted content or live interview responses. If we determine that AI is being used outside these guidelines, we reserve the right to pause or end the interview, and your candidacy may be disqualified. Trade Secret Notice By submitting an application, you agree not to disclose to Samsung—or encourage Samsung to use—any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity. Applicant Privacy Policy semiconductor.samsung.com

Requirements

Must-haves

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
Advancing the World’s Technology Together
Location: Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.
What You’ll Do
Develop RTL (Verilog/SystemVerilog) for the IO die, integrating UCIe, PCIe, and other high-speed interconnect IP into a cohesive chiplet-based architecture.
Integrate internal and third-party interconnect IP — UCIe, PCIe, CXL, die-to-die, and NoC — into the IO die, including configuration, glue logic, clock/reset, and interface bridging.
Modify and customize PCIe and other interconnect IP as needed — controller, PIPE/PHY interface, and configuration logic — to meet die-level requirements and close functional gaps.
Define and implement die-to-die and chiplet interfaces using UCIe, ensuring protocol compliance and interoperability across chiplets.
Own the microarchitecture and RTL for IO subsystems such as PCIe/CXL controllers, UCIe adapters, and interconnect fabric bridges.
Collaborate with verification engineers to develop test plans and debug functional issues at the IP, subsystem, and die level.
Work with architecture, PHY/SerDes, physical design, and software teams to close requirements across performance, power, area, and interoperability.
Make design decisions out of a large design trade-off space across performance, power, latency, bandwidth, and cost.
Develop and automate IP integration and RTL assembly flows using scripting and agentic AI tools and frameworks to improve turnaround time and quality of results.
Communicate effectively with stakeholders, including users, partners, and management, to ensure that the die is delivered on time and within budget.
Complete other responsibilities as assigned.
Bachelor’s with 5+ years, or Master’s with 3+ years, or PhD's with 0+ years of industry experience.
Strong background in microarchitecture and RTL design for complex SoC and die integration.
5+ years of experience in RTL development (Verilog/SystemVerilog) for high-speed interconnect and IO subsystems.
Hands-on experience integrating and configuring interconnect IP such as PCIe, CXL, UCIe, and die-to-die interfaces.
Experience modifying or customizing third-party interconnect IP (e.g., PCIe controller, PIPE, or PHY interface) to meet die-level requirements.
Familiarity with UCIe and chiplet-based, multi-die architectures and die-to-die interconnect.
Solid understanding of PCIe/CXL protocol stacks (transaction, data link, and physical layers) and the PIPE interface.
Experience with SoC integration methodologies, IP packaging (e.g., IP-XACT), and on-chip interface protocols such as AXI, ACE, CHI, or APB.

Nice-to-haves

Proficiency in scripting (Tcl, Python, or Perl) for design integration and automation; familiarity with agentic AI tools and frameworks is a plus.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aimlpythonrest

Platform: greenhouse
Effort: quick

Benefits

Benefits detected in the listing.

Dental

Vision

401k

Paid Time Off

Wellness