Job description

L3Harris is dedicated to recruiting and developing high-performing talent who are passionate about what they do. Our employees are unified in a shared dedication to our customers’ mission and quest for professional growth. L3Harris provides an inclusive, engaging environment designed to empower employees and promote work-life success. Fundamental to our culture is an unwavering focus on values, dedication to our communities, and commitment to excellence in everything we do. L3Harris is the Trusted Disruptor in defense tech. With customers’ mission-critical needs always in mind, our employees deliver end-to-end technology solutions connecting the space, air, land, sea and cyber domains in the interest of national security. Job Title: Lead, FPGA Verification, UVM Job Code: 44204 Job Location : Palm Bay, FL Job Schedule: 9/80: Employees work 9 out of every 14 days – totaling 80 hours worked – and have every other Friday off Job Description : Seeking talented UVM/Design Verification Engineer, able to work in teams and independently, learn quickly, and be productive in a fast-paced, dynamic environment. The ideal candidate will have experience developing and executing verification plans, building reusable UVM-based testbenches, and creating constrained-random and directed tests to validate complex digital designs. Responsibilities include debugging simulation failures, analyzing coverage metrics, collaborating closely with design and systems engineers, and ensuring functional correctness throughout the development lifecycle. Candidates should demonstrate strong problem-solving skills, familiarity with industry-standard EDA tools, and the ability to clearly communicate technical issues and solutions. Experience with SystemVerilog, assertion-based verification, scripting languages, and regression automation is highly desirable. Essential Functions: • Execute and contribute to the FPGA verification plan • Architect UVM test cases for individual blocks or sub blocks within an FPGA • Develop reusable agents, top level testbench modules and environments • Define and implement functional coverage model based upon DUT requirements and close code coverage. • Utilize UVM to create drivers, monitors, predictors, and scoreboards based on DUT requirements. • Strong understanding of FPGA design process including requirements generation, preliminary design, peer reviews, detailed design, test plan generation, and integration and test. • Work independently or with limited guidance to develop test bench solutions. • Familiarity with test scoping for complex designs, code coverage, functional coverage, assertions. • Ability to focus on finding design issues, corner cases and out of box ideas to make designs more robust. • Ability to obtain US government clearance. Qualifications : • Bachelor’s Degree and minimum 9 years of prior relevant experience. Graduate Degree and a minimum of 7 years of prior related experience. In lieu of a degree, minimum of 13 years of prior related experience. Preferred Additional Skills: • Experience with and understanding of Altera or Xilinx / AMD FPGA architectures • Experience with high speed serial protocols (PCI Express, SRIO, Ethernet) • Experience designing 10G Ethernet based Network Interface Designs • Experience in network protocols including IPv6 and UDP • Experience with SoC (Kintex UltraScale/UltraScale+, Virtex UltraScale/UltraScale+, Zynq UltraScale) • Experience with VHDL • Experience in ASIC / FPGA verification using C/C++ and/or System Verilog • Experience with DO-254 air worthiness certification • Experience with building and setting up scalable simulation/verification environments. • Experience with and understanding of Altera and/or Xilinx FPGA architectures. • Experience with Vivado and/or Quartus tool suite. • Proficiency with hardware verification languages: System Verilog, System Verilog Assertions • Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc. • Proficient in scripting languages: bash/csh, Perl, Python, etc. • Revision Control Systems: svn, git • Proficient in Linux Environments • Constrained Random Verification Experience highly desired. • Experience with packet-based protocols (PCI Express etc.), Network-centric designs (Ethernet, IP, FC). • Experience with high speed memory interfaces (DDRx) #LI-KT1 L3Harris Technologies is proud to be an Equal Opportunity Employer. L3Harris is committed to treating all employees and applicants for employment with respect and dignity and maintaining a workplace that is free from unlawful discrimination. All applicants will be considered for employment without regard to race, color, religion, age, national origin, ancestry, ethnicity, gender (including pregnancy, childbirth, breastfeeding or other related medical conditions), gender identity, gender expression, sexual orientation, marital status, veteran status, disability, genetic information, citizenship status, characteristic or membership in any other group protected by federal, state or local laws. L3Harris maintains a drug-free workplace and performs pre-employment substance abuse testing and background checks, where permitted by law. Please be aware many of our positions require the ability to obtain a security clearance. Security clearances may only be granted to U.S. citizens. In addition, applicants who accept a conditional offer of employment may be subject to government security investigation(s) and must meet eligibility requirements for access to classified information. By submitting your resume for this position, you understand and agree that L3Harris Technologies may share your resume, as well as any other related personal information or documentation you provide, with its subsidiaries and affiliated companies for the purpose of considering you for other available positions. L3Harris Technologies is an E-Verify Employer. Please click here for the E-Verify Poster in English or Spanish . For information regarding your Right To Work, please click here for English or Spanish .

Requirements

Must-haves

Job Title: Lead, FPGA Verification, UVM
Job Code: 44204
Job Location : Palm Bay, FL
Job Schedule: 9/80: Employees work 9 out of every 14 days – totaling 80 hours worked – and have every other Friday off
Execute and contribute to the FPGA verification plan
Architect UVM test cases for individual blocks or sub blocks within an FPGA
Develop reusable agents, top level testbench modules and environments
Define and implement functional coverage model based upon DUT requirements and close code coverage.
Utilize UVM to create drivers, monitors, predictors, and scoreboards based on DUT requirements.
Strong understanding of FPGA design process including requirements generation, preliminary design, peer reviews, detailed design, test plan generation, and integration and test.
Work independently or with limited guidance to develop test bench solutions.
Familiarity with test scoping for complex designs, code coverage, functional coverage, assertions.
Ability to focus on finding design issues, corner cases and out of box ideas to make designs more robust.
Ability to obtain US government clearance.
Bachelor’s Degree and minimum 9 years of prior relevant experience. Graduate Degree and a minimum of 7 years of prior related experience. In lieu of a degree, minimum of 13 years of prior related experience.
Experience with and understanding of Altera or Xilinx / AMD FPGA architectures
Experience with high speed serial protocols (PCI Express, SRIO, Ethernet)
Experience designing 10G Ethernet based Network Interface Designs
Experience in network protocols including IPv6 and UDP
Experience with SoC (Kintex UltraScale/UltraScale+, Virtex UltraScale/UltraScale+, Zynq UltraScale)
Experience with VHDL
Experience in ASIC / FPGA verification using C/C++ and/or System Verilog
Experience with DO-254 air worthiness certification
Experience with building and setting up scalable simulation/verification environments.

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: career-feeds
Effort: medium

Benefits

Benefits detected in the listing.

Vision

Pto