Job description

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering ( SCHIE ) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Shared and Custom IP & Silicon (SCIPS) team is instrumental in defining and elivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Senior Design Verification Engineer to join the team to support our mission as a key role with block and sub-system level verification. #SCHIE #CSME #SCIPS Responsibilities The candidate for this position will be expected and able to complete the following responsibilities: • Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of custom Intellectual Property (IP) components • Define pre-Si verification (simulation/emulation/FPGA-testing) and post-Si validation strategies and develop test-plans • Execute end-to-end verification plans at block, sub-system or system level • Expertise in UVM based verification methodology including coverage closure • Basic C, C++ programming understanding to develop C based testbenches • Silicon validation test planning, silicon bring-up and validation activities. • Collaborate across verification teams on vertical and horizontal reuse of components. • Interact with Architecture, Design, Firmware/Software, Product Engineering, Program Management and third party vendor teams to ensure pre-and-post-Si testing is comprehensive • Provide technical leadership through mentorship and teamwork. • Adopt new AI based tools and agents for efficient execution Qualifications Required Qualifications: • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. Other Requirements • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. • Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Preferred Qualifications: • B.S. or higher in Computer Engineering, Electrical Engineering, or similar. • 7+ years of experience in design verification, developing test plans, creating verification environments, creating test content, and debugging for multiple IPs, sub-systems and or System on Chips(SOCs). • 3+ years of experience in silicon bring-up, post-silicon validation for complex Application Specific Integrated Circuits(ASIC) or System on Chip(SOC). • Extensive experience in block level and sub-system level end-to-end verification, including test-plan development, execution, and debugging. • Experienced in UVM based testbench development and execution • Hold on C/C++ programming and experience in developing and debugging C based test infrastructure • Experience in developing test FW for any industry standard processors including, boot flow, interrupt handling, memory allocation • In depth knowledge of verification principles, testbenches, stimulus generation, coverage based verification, coverage closure • Experience in chip bring-up and silicon validation for complex SoC • Solid understanding of chip and/or computer architecture • Communication skills and works with the team in a collaborative setting • Energetic and self-motivated • Can come up with innovative solutions using AI • Experience in formal verification using Jasper Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: careers.microsoft.com This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Requirements

Must-haves

We are looking for a Senior Design Verification Engineer to join the team to support our mission as a key role with block and sub-system level verification.
The candidate for this position will be expected and able to complete the following responsibilities:
Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of custom Intellectual Property (IP) components
Define pre-Si verification (simulation/emulation/FPGA-testing) and post-Si validation strategies and develop test-plans
Execute end-to-end verification plans at block, sub-system or system level
Expertise in UVM based verification methodology including coverage closure
Basic C, C++ programming understanding to develop C based testbenches
Silicon validation test planning, silicon bring-up and validation activities.
Collaborate across verification teams on vertical and horizontal reuse of components.
Interact with Architecture, Design, Firmware/Software, Product Engineering, Program Management and third party vendor teams to ensure pre-and-post-Si testing is comprehensive
Provide technical leadership through mentorship and teamwork.
Adopt new AI based tools and agents for efficient execution

Nice-to-haves

B.S. or higher in Computer Engineering, Electrical Engineering, or similar.
Extensive experience in block level and sub-system level end-to-end verification, including test-plan development, execution, and debugging.
Experienced in UVM based testbench development and execution
Hold on C/C++ programming and experience in developing and debugging C based test infrastructure
Experience in developing test FW for any industry standard processors including, boot flow, interrupt handling, memory allocation
In depth knowledge of verification principles, testbenches, stimulus generation, coverage based verification, coverage closure
Experience in chip bring-up and silicon validation for complex SoC
Solid understanding of chip and/or computer architecture
Communication skills and works with the team in a collaborative setting
Energetic and self-motivated
Can come up with innovative solutions using AI
Experience in formal verification using Jasper

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

azureai

Platform: eightfold
Effort: medium

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