Job description

Standard Job Description You will be the ASIC & FPGA Design Engineer for the ASIC/FPGA department at Lockheed  Martin  Missiles  and  Fire  Control. Our team creates FPGA‑based architectures that power current and next‑generation defense systems, delivering highly reliable, high‑performance digital solutions for mission‑critical applications. What You Will Be Doing As the FPGA Design Engineer you will lead the digital development of Missile platforms, partnering with algorithm, software, and hardware groups to transform MATLAB/Simulink models into efficient, synthesizable RTL and integrate that RTL onto AMD RFSoC and Versal devices. Your responsibilities will include: • Defining digital architectures that meet radar/RF‑sensor performance, power, and timing requirements. • Converting algorithmic models from MATLAB/Simulink into high‑level synthesis (Vitis HLS) and RTL code (VHDL/Verilog/SystemVerilog). • Writing, simulating, and verifying RTL and HLS implementations, using self‑checking testbenches and functional coverage. • Integrating custom and third‑party IP blocks, managing clock‑domain crossing and timing‑closure challenges with Synopsys VCS and Xilinx Vivado tools. • Performing place‑and‑route, timing analysis, and optimization to achieve timing closure on RFSoC/Versal platforms. • Conducting design reviews, delivering clear documentation, and maintaining configuration control in version‑control systems. • Collaborating with algorithm developers, hardware engineers, and software teams to ensure seamless end‑to‑end system integration. • Leading mentorship efforts for junior engineers and fostering an inclusive, innovative team culture. • Supporting system‑level validation, debugging, and board‑level testing to confirm functional and performance goals. Why Join Us Do you want to be part of a company culture that empowers employees to think big, lead with a growth mindset, and make the impossible a reality? We provide the resources and give you the flexibility to enable inspiration and focus. If you have the passion and courage to dream big, work hard, and have fun doing what you love then we want to build a better tomorrow with you. We offer flexible work schedules to comprehensive benefits investing in your future and security. Learn more about Lockheed Martin’s comprehensive benefits package here. Further Information About This Opportunity: This position is in Orlando, FL. Discover more about our Orlando, Florida location. MUST BE A U.S. CITIZEN - This position is located at a facility that requires special access. The selected candidate must be able to obtain a secret clearance. An active Secret clearance is required to start. Basic Qualifications • B.S. or M.S. in Electrical/Computer Engineering or a related field • Proficiency in VHDL, Verilog, or SystemVerilog • Experience with FPGA simulation tools such as Synopsys VCS • Proficiency with timing analysis, clock-domain crossing, and IP integration Desired Skills • Experience converting Simulink/MATLAB models into synthesizable code using Vivado HLS • Experience with AMD RFSoC and Versal families • Experience implementing filters, FFTs, beamforming, and other RF-DSP algorithms in hardware • Experience with the MFC DAR process • Knowledge of software programming languages such as C, C++, or Python • Prior work on radar, RF sensor, or high-frequency digital systems • Leadership experience supporting design reviews, mentoring engineers, or providing cross-functional technical guidance • Experience with missile applications Pay Information Full-Time Salary Range: $98100.00 - $182100.00 At Lockheed Martin, we know mission success starts with taking care of our people. Our Total Rewards program is designed to attract top talent, support your well-being, and help you grow—both professionally and personally. The salary range for this position is as listed on the requisition. Please note that the salary information listed is a general guideline only. Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market(work location) and business considerations when extending an offer. Benefits offered: Medical, Dental, Vision, Flexible work arrangements and schedules (e.g., 4x10), 401(k) match, Paid time off, Holidays, Parental Leave, EAP, Flexible Spending Accounts, Education Assistance, Life Insurance, Short-Term Disability, and Long-Term Disability. • Annual short-term and/or long-term incentive compensation programs may be offered depending on the position. Payments under these annual programs are not guaranteed and can vary from year to year and are tied to a range of performance metrics. • For (Washington state applicants only) Non-represented full-time employees: accrue at least 10 hours per month of Paid Time Off (PTO) to be used for incidental absences and other reasons; receive at least 90 hours for holidays. Represented full time employees accrue 6.67 hours of Vacation per month; accrue up to 52 hours of sick leave annually; receive at least 96 hours for holidays. PTO, Vacation, sick leave, and holiday hours are prorated based on start date during the calendar year.

Requirements

Must-haves

Standard Job Description
What You Will Be Doing
Defining digital architectures that meet radar/RF‑sensor performance, power, and timing requirements.
Converting algorithmic models from MATLAB/Simulink into high‑level synthesis (Vitis HLS) and RTL code (VHDL/Verilog/SystemVerilog).
Writing, simulating, and verifying RTL and HLS implementations, using self‑checking testbenches and functional coverage.
Integrating custom and third‑party IP blocks, managing clock‑domain crossing and timing‑closure challenges with Synopsys VCS and Xilinx Vivado tools.
Performing place‑and‑route, timing analysis, and optimization to achieve timing closure on RFSoC/Versal platforms.
Conducting design reviews, delivering clear documentation, and maintaining configuration control in version‑control systems.
Collaborating with algorithm developers, hardware engineers, and software teams to ensure seamless end‑to‑end system integration.
Leading mentorship efforts for junior engineers and fostering an inclusive, innovative team culture.
Supporting system‑level validation, debugging, and board‑level testing to confirm functional and performance goals.
This position is in Orlando, FL. Discover more about our Orlando, Florida location.
MUST BE A U.S. CITIZEN - This position is located at a facility that requires special access. The selected candidate must be able to obtain a secret clearance. An active Secret clearance is required to start.
B.S. or M.S. in Electrical/Computer Engineering or a related field
Proficiency in VHDL, Verilog, or SystemVerilog

Nice-to-haves

Experience converting Simulink/MATLAB models into synthesizable code using Vivado HLS
Experience with AMD RFSoC and Versal families
Experience implementing filters, FFTs, beamforming, and other RF-DSP algorithms in hardware
Experience with the MFC DAR process
Knowledge of software programming languages such as C, C++, or Python
Prior work on radar, RF sensor, or high-frequency digital systems
Leadership experience supporting design reviews, mentoring engineers, or providing cross-functional technical guidance
Experience with missile applications
Pay Information

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Benefits

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Dental

Vision

401(K)

Pto

Paid Time Off

Parental Leave