Job description

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits Learn more about benefits at Google . • Define the detailed microarchitecture specifications for silicon su bsystems and small to medium-sized intellectual property blocks to meet performance, area, and power requirements. • Integrate internal and external intellectual property (IP) blocks seaml essly into complex silicon designs and multi-component subsystems. • Execute production-grade RTL coding, debug intricate function and perfor mance simulation issues, and conduct standard lint, clock domain crossing, formal verification, and unified power format checks. • Partne r closely with validation teams during test plan formulation and coverage analysis for comprehensive subsystem and chip-level design verification. • Drive technical alignment across multi-disciplinary and multi-site engineering groups to resolve architectural issues and ensure successful product delivery. • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. • 8 years of experience with IP Development or Integration. • Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language). • Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language). Minimum qualifications: • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. • 8 years of experience with IP Development or Integration. • Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language). • Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language). Preferred qualifications: • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. • Experience with ASIC design methodologies for clock domain checks, reset checks, and low power design. • Knowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset. • Knowledge of high-performance and low-power design techniques. • Knowledge of ASIC Verification, DFT, synthesis, STA, or physical design. • Knowledge of FPGA and emulation platforms.

Requirements

Must-haves

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
Learn more about benefits at Google .
Define the detailed microarchitecture specifications for silicon su bsystems and small to medium-sized intellectual property blocks to meet performance, area, and power requirements.
Integrate internal and external intellectual property (IP) blocks seaml essly into complex silicon designs and multi-component subsystems.
Execute production-grade RTL coding, debug intricate function and perfor mance simulation issues, and conduct standard lint, clock domain crossing, formal verification, and unified power format checks.
Partne r closely with validation teams during test plan formulation and coverage analysis for comprehensive subsystem and chip-level design verification.
Drive technical alignment across multi-disciplinary and multi-site engineering groups to resolve architectural issues and ensure successful product delivery.
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with IP Development or Integration.
Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language).
Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language).
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with IP Development or Integration.
Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language).
Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language).

Nice-to-haves

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with ASIC design methodologies for clock domain checks, reset checks, and low power design.
Knowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.
Knowledge of high-performance and low-power design techniques.
Knowledge of ASIC Verification, DFT, synthesis, STA, or physical design.
Knowledge of FPGA and emulation platforms.

Application prep

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Keywords to mirror

Platform: google
Effort: medium