Principal Engineer Memory Architect at MaxLinear

Job description

MaxLinear is seeking a Principal Engineer Memory Architect to join our team. In this role, you will focus on the following: • Design, define, evaluate, and optimize memory intellectual property across advanced technology nodes • Leverage your memory architecture expertise, circuit-level understanding, and system-level awareness to deliver high-performance, power-efficient, area-optimized, and reliable memory solutions for SoC integration • Work closely with IP and SoC teams to provide technical direction for memory IP roadmaps, architecture selection, compiler evaluation, and trade-off decisions involving PPA and robustness • Own the design and optimization of memory architectures, based on SRAMs, ROMs, and register files, using memory compilers or custom designs • Deliver competitive memory IP solutions and enabling seamless integration into SoCs • Collaborate with cross-functional engineering teams and external IP vendors, and developing scalable QA methodologies, automation flows, and verification frameworks for consistent memory IP evaluation • Deep understanding of embedded SRAM and register-file architectures, including bit-cell fundamentals, array layout considerations, and PPA trade-offs • Strong knowledge of low-power techniques, read/write assist techniques, design stability and robustness, design margining and power integrity considerations • Experience analyzing memory behavior across PVT corners and evaluating timing, reliability, signal integrity, and SoC-level trade-offs • Strong understanding of memory compiler flows and verification methodologies, with the ability to assess both compiled and custom memory solutions • Excellent communication skills and ability to collaborate effectively across multidisciplinary teams and influence technical decisions at both strategic and hands-on levels • Preferred Qualifications • Proficiency with EDA and analysis tools HSPICE, Spectre, Python, and related memory verification or modeling environments • Familiarity with SoC design flows and interactions among memory IP, standard cells, I/O libraries, clocking, system buses, and interface protocols • Familiarity with ROMs, flash memories, OTPs is a plus • Understanding of advanced-node scaling, PVT variation impacts, memory behavior across corners, and silicon validation practices • Familiarity with transistor-level circuit design and analysis, and experience using IC design or simulation tools such as HSPICE, Spectre, or Cadence Virtuoso, is a plus • Experience with QA methodologies, validation frameworks, technical roadmaps • BS in Electrical Engineering or related + 9 years of experience, or MS + 7 years of experience, or Ph.D. + 4 years of experience MaxLinear has a Total Compensation philosophy which includes base salary and annual discretionary bonus eligibility and many positions also include stock-based compensation. MaxLinear's good faith estimate starting base salary range is: $135,000 to $ 198,000 Annually We offer competitive benefits designed to support employee health, welfare, and retirement and some highlights are: health care benefits, 401k savings plan, Employee Stock Purchase Plan (ESPP), and paid time off. The actual starting base salary will be determined by the match to certain role-related criteria such as educational degree(s) or equivalent, relevant work experience, skillset needed for the role, and geographic location; this is not an all-inclusive list as some roles may require unique skills or experience. Qualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race, sex, religion, national origin, sexual orientation, gender identity, disability, or protected veteran status. MaxLinear is a global, NASDAQ-traded company (MXL) where the entrepreneurial spirit is alive and well. We are a fabless system-on-chip product company, striving to improve the world’s communication networks for everyone through our highly integrated radio-frequency (RF), analog, digital, and mixed-signal semiconductor solutions for access and connectivity, wired and wireless infrastructure, and industrial and multi-market applications. We hire the best people in the industry and engage them in some of the most exciting opportunities that connect the world we live in today. Our growth has come from innovative, bold approaches to solving some of the world’s most challenging communication technology problems in the most efficient and effective manner. MaxLinear began by developing the world’s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn’t achieve the extremely high-performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we’ve developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments. Over the years, we’ve expanded through organic growth and through several acquisitions that have perfectly complemented our existing portfolio and enabled us to deliver complete end-to-end solutions in our target markets. One such example was the acquisition of Intel’s Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers’ needs. Our headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Valencia, Spain; Bangalore, India; Munich, Germany; Israel; and Singapore. We have approximately 1,200 employees, a substantial majority of whom have engineering degrees and include masters and Ph.D. graduates from many of the premiere universities around the world. Our employees thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building the best and most innovative products on the market. We can recommend jobs specifically for you! Click here to get started.

Requirements

Must-haves

MaxLinear is seeking a Principal Engineer Memory Architect to join our team. In this role, you will focus on the following:
Design, define, evaluate, and optimize memory intellectual property across advanced technology nodes
Leverage your memory architecture expertise, circuit-level understanding, and system-level awareness to deliver high-performance, power-efficient, area-optimized, and reliable memory solutions for SoC integration
Work closely with IP and SoC teams to provide technical direction for memory IP roadmaps, architecture selection, compiler evaluation, and trade-off decisions involving PPA and robustness
Own the design and optimization of memory architectures, based on SRAMs, ROMs, and register files, using memory compilers or custom designs
Deliver competitive memory IP solutions and enabling seamless integration into SoCs
Collaborate with cross-functional engineering teams and external IP vendors, and developing scalable QA methodologies, automation flows, and verification frameworks for consistent memory IP evaluation
Deep understanding of embedded SRAM and register-file architectures, including bit-cell fundamentals, array layout considerations, and PPA trade-offs
Strong knowledge of low-power techniques, read/write assist techniques, design stability and robustness, design margining and power integrity considerations
Experience analyzing memory behavior across PVT corners and evaluating timing, reliability, signal integrity, and SoC-level trade-offs
Strong understanding of memory compiler flows and verification methodologies, with the ability to assess both compiled and custom memory solutions
Excellent communication skills and ability to collaborate effectively across multidisciplinary teams and influence technical decisions at both strategic and hands-on levels
Familiarity with SoC design flows and interactions among memory IP, standard cells, I/O libraries, clocking, system buses, and interface protocols
Understanding of advanced-node scaling, PVT variation impacts, memory behavior across corners, and silicon validation practices
Experience with QA methodologies, validation frameworks, technical roadmaps
BS in Electrical Engineering or related + 9 years of experience, or MS + 7 years of experience, or Ph.D. + 4 years of experience
Our headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Valencia, Spain; Bangalore, India; Munich, Germany; Israel; and Singapore.
We can recommend jobs specifically for you!
Click here to get started.

Nice-to-haves

Preferred Qualifications • Proficiency with EDA and analysis tools HSPICE, Spectre, Python, and related memory verification or modeling environments
Familiarity with ROMs, flash memories, OTPs is a plus
Familiarity with transistor-level circuit design and analysis, and experience using IC design or simulation tools such as HSPICE, Spectre, or Cadence Virtuoso, is a plus

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Keywords to mirror

python

Platform: icims
Effort: medium

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