Job description

Job Details: Job Description: About the Role Join Intel s architecture team as a Senior CPU Silicon Analysis Engineer. In this role, you will be central to in-depth studies of CPU designs, providing critical data-driven guidance for future CPU roadmap decisions. You will own silicon bring-up, maintenance, and a wide range of measurements to characterize processor behavior across power, performance, and physical operating conditions. Your findings will directly influence architectural decisions at the highest levels of Intel s CPU development organization. Key Responsibilities Own and operate lab infrastructure for systematic silicon characterization, including bring-up, maintenance, and debug of pre-production and production platforms Plan and execute measurements across a broad range of metrics including performance, IPC, power, dynamic capacitance, leakage, voltage-frequency curves, and microarchitectural telemetry Design and execute structured measurement campaigns to characterize silicon behavior under a variety of operating conditions, workloads, and thermal/power envelopes Analyze and interpret silicon data to identify power/performance gaps, anomalies, and opportunities relative to architectural expectations and roadmap targets Collaborate with architecture, benchmarking, backend design, and simulation teams to correlate lab results with pre-silicon models and design data, and to drive root cause analysis of discrepancies Develop tooling, scripts, and automation to streamline data collection, processing, and reporting pipelines Communicate findings clearly through technical reports and presentations to engineering leadership and cross-functional stakeholders To Be Successful in This Role, You Should Demonstrate A methodical, detail-oriented approach to lab work and data analysis, with the discipline to maintain accuracy across complex, multi-dimensional data sets Strong collaborative instincts and the ability to work effectively across architecture, design, and simulation teams to drive alignment and root cause resolution Clear and confident communication skills, with the ability to translate technical findings into actionable insights for both engineering peers and leadership audiences Qualifications: Minimum Qualifications Bachelor s Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline with 8 years of relevant industry experience, OR a Master s Degree in a related discipline with 6 years of relevant industry experience Hands-on experience with silicon lab environments, including platform bring-up, debug, and instrumentation Experience collecting and analyzing silicon power and performance metrics such as IPC, Frequency, Cdyn, leakage, and microarchitectural telemetries Proficiency in scripting languages (Python, Bash, or similar) for test automation and data analysis Strong analytical skills and ability to draw actionable conclusions from complex, multi-dimensional silicon data sets Preferred Qualifications Experience characterizing CPU silicon across a range of designs and operating conditions Familiarity with EMON/PMU-based performance profiling and OS-level performance tooling Understanding of CPU microarchitecture sufficient to interpret performance counter data and correlate measurements to architectural behavior Exposure to backend design concepts such as voltage-frequency corner selection, leakage-frequency tradeoffs, and process library characteristics Experience with RTL simulation or pre-silicon performance modeling and correlation workflows Background in silicon-based benchmarking and performance characterization of processor designs Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Requirements

Must-haves

Key Responsibilities Own and operate lab infrastructure for systematic silicon characterization, including bring-up, maintenance, and debug of pre-production and production platforms
Plan and execute measurements across a broad range of metrics including performance, IPC, power, dynamic capacitance, leakage, voltage-frequency curves, and microarchitectural telemetry
Design and execute structured measurement campaigns to characterize silicon behavior under a variety of operating conditions, workloads, and thermal/power envelopes
Analyze and interpret silicon data to identify power/performance gaps, anomalies, and opportunities relative to architectural expectations and roadmap targets
Collaborate with architecture, benchmarking, backend design, and simulation teams to correlate lab results with pre-silicon models and design data, and to drive root cause analysis of discrepancies
Develop tooling, scripts, and automation to streamline data collection, processing, and reporting pipelines
Communicate findings clearly through technical reports and presentations to engineering leadership and cross-functional stakeholders
To Be Successful in This Role, You Should Demonstrate A methodical, detail-oriented approach to lab work and data analysis, with the discipline to maintain accuracy across complex, multi-dimensional data sets
Strong collaborative instincts and the ability to work effectively across architecture, design, and simulation teams to drive alignment and root cause resolution
Clear and confident communication skills, with the ability to translate technical findings into actionable insights for both engineering peers and leadership audiences
Qualifications: Minimum Qualifications
Hands-on experience with silicon lab environments, including platform bring-up, debug, and instrumentation
Experience collecting and analyzing silicon power and performance metrics such as IPC, Frequency, Cdyn, leakage, and microarchitectural telemetries
Proficiency in scripting languages (Python, Bash, or similar) for test automation and data analysis
Strong analytical skills and ability to draw actionable conclusions from complex, multi-dimensional silicon data sets

Nice-to-haves

Experience characterizing CPU silicon across a range of designs and operating conditions
Familiarity with EMON/PMU-based performance profiling and OS-level performance tooling
Understanding of CPU microarchitecture sufficient to interpret performance counter data and correlate measurements to architectural behavior
Exposure to backend design concepts such as voltage-frequency corner selection, leakage-frequency tradeoffs, and process library characteristics
Experience with RTL simulation or pre-silicon performance modeling and correlation workflows
Background in silicon-based benchmarking and performance characterization of processor designs
Job Type: Experienced Hire
Shift: Shift 1 (United States of America)
Primary Location: US, Oregon, Hillsboro

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Platform: workday
Effort: long