As a Staff Implementation Engineer in Arm's Solutions Engineering group, you will play a key role in delivering sophisticated CPU, GPU, interconnect and SoC designs from RTL through GDSII and tapeout.
This is a senior, hands-on Physical Design role requiring strong technical depth across the complete implementation flow and the ability to independently drive designs through timing, power, physical and signoff closure!
Responsibilities:
• Own and drive end-to-end RTL-to-GDSII physical implementation of sophisticated processor cores, graphics units, communication fabrics, subsystems, and SoC builds through tapeout!
• Collaborate directly with RTL and architecture teams to understand build intent and translate architectural and PPA requirements into implementation targets.
• Drive timing closure across MCMM scenarios , including setup, hold, clocking and complex timing-path analysis.
• Own physical implementation readiness and closure across STA, physical verification, power integrity and other tapeout signoff requirements .
• Work closely with DFT teams to ensure scan, test modes and other DFT requirements are correctly implemented and closed.
• Debug complex implementation and EDA-tool issues and work with EDA vendors and internal methodology teams to drive resolution.
• Drive implementation reviews, identify risks early and develop mitigation plans to ensure successful tapeout.
• Develop and improve implementation methodologies, automation and flows to increase design quality and execution efficiency..
• Collaborate optimally across geographically distributed teams and drive issues to closure with minimal direction.
Required Skills and Experience :
• Bachelor's degree or equivalent experience, meaningful professional experience, or Master's degree, along with comparable practical experience, in Electrical Engineering, Computer Engineering, or a related technical field.
• 10+ years of hands-on ASIC Physical Build / Implementation experience, with demonstrated ownership of complex builds spanning from RTL to GDSII and successful tapeout.
• Deep hands-on expertise spanning the full implementation lifecycle, including:
Synthesis and design optimization
Floorplanning and physical partitioning
Power delivery network (PDN) planning
Placement and congestion optimization
Clock tree synthesis and clock optimization
Routing and post-route optimization
• Solid grasp of MCMM timing closure, timing constraints, clocking, OCV methodologies, crosstalk/SI and advanced-node timing challenges.
• In-depth knowledge of low-power implementation, including UPF, multiple voltage domains, power gating, level shifters, isolation and voltage/frequency scaling.
• Strong scripting and automation skills using Tcl, Python, Perl, shell and/or Make .
“Nice To Have” Skills and Experience :
• Experience implementing high-performance Arm CPUs, GPUs, coherent interconnects or complex SoCs .
• Proven familiarity with sophisticated process nodes and large, high-frequency builds.
• Experience with hierarchical physical design and integration of multiple sophisticated IPs/subsystems.
• Experience with structured clock architectures and complex clock-distribution methodologies.
• Experience working directly with foundries, EDA vendors and Physical IP providers on implementation and signoff issues.
In Return:
We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and build outstanding:
• Partner and customer focus
• Teamwork and communication
• Creativity and innovation
• Team and personal development
• Impact and influence
• Deliver on your promises
Salary Range:
$198,100-$268,000 per year We value people as individuals and our dedication is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process.
Our 10x Mindset
At Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: careers.arm.com
Use of AI in Your Application
At Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.
Recruitment Adjustments and Accommodations
At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.
Hybrid Working
Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.
Equal Opportunities
Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
Requirements
Must-haves
As a Staff Implementation Engineer in Arm's Solutions Engineering group, you will play a key role in delivering sophisticated CPU, GPU, interconnect and SoC designs from RTL through GDSII and tapeout.
This is a senior, hands-on Physical Design role requiring strong technical depth across the complete implementation flow and the ability to independently drive designs through timing, power, physical and signoff closure!
Own and drive end-to-end RTL-to-GDSII physical implementation of sophisticated processor cores, graphics units, communication fabrics, subsystems, and SoC builds through tapeout!
Collaborate directly with RTL and architecture teams to understand build intent and translate architectural and PPA requirements into implementation targets.
Drive timing closure across MCMM scenarios , including setup, hold, clocking and complex timing-path analysis.
Own physical implementation readiness and closure across STA, physical verification, power integrity and other tapeout signoff requirements .
Work closely with DFT teams to ensure scan, test modes and other DFT requirements are correctly implemented and closed.
Debug complex implementation and EDA-tool issues and work with EDA vendors and internal methodology teams to drive resolution.
Drive implementation reviews, identify risks early and develop mitigation plans to ensure successful tapeout.
Develop and improve implementation methodologies, automation and flows to increase design quality and execution efficiency..
Collaborate optimally across geographically distributed teams and drive issues to closure with minimal direction.
10+ years of hands-on ASIC Physical Build / Implementation experience, with demonstrated ownership of complex builds spanning from RTL to GDSII and successful tapeout.
Deep hands-on expertise spanning the full implementation lifecycle, including:
Synthesis and design optimization
Floorplanning and physical partitioning
Power delivery network (PDN) planning
Placement and congestion optimization
Clock tree synthesis and clock optimization
Routing and post-route optimization
Solid grasp of MCMM timing closure, timing constraints, clocking, OCV methodologies, crosstalk/SI and advanced-node timing challenges.
In-depth knowledge of low-power implementation, including UPF, multiple voltage domains, power gating, level shifters, isolation and voltage/frequency scaling.
Strong scripting and automation skills using Tcl, Python, Perl, shell and/or Make .
Experience implementing high-performance Arm CPUs, GPUs, coherent interconnects or complex SoCs .
Nice-to-haves
“Nice To Have” Skills and Experience :
Application prep
Use the role’s language and application details while tailoring your materials.