Job description

Standard Job Description You will be the ASIC & FPGA Design Engineer for the Hardware Engineering team at Lockheed Martin  Missiles and Fire Control (MFC). Our team delivers precision engagement aerospace and defense systems, designing, building and fielding the electrical hardware that powers missiles, sensors and other mission critical subsystems for the United States and allied militaries. What You Will Be Doing As the ASIC & FPGA Design Engineer Sr Stf you will own the full physical-design flow — from floorplan through tape-out — serving as the technical lead who turns schematic intent into high-performance, parasitic-aware physical designs across a portfolio of programs. You will operate in a dual-tool environment (Synopsys Custom Compiler and Cadence Virtuoso) and drive physical-verification closure across multiple foundries in direct support of mission-critical programs. Your responsibilities will include: • Leading full-custom analog and mixed-signal layout across multiple programs, from floorplan through place-and-route of analog blocks, optimizing area, device matching, signal integrity, and power delivery • Owning the physical-design technical strategy for device generations from 130 nm to 12 nm, including high-voltage BCD processes, and driving layout methodology standardization across the department Why Join Us Do you want to be part of a company culture that empowers employees to think big, lead with a growth mindset, and make the impossible a reality? We provide the resources and give you the flexibility to enable inspiration and focus. If you have the passion and courage to dream big, work hard, and have fun doing what you love then we want to build a better tomorrow with you. We offer flexible work schedules to comprehensive benefits investing in your future and security. Learn more about Lockheed Martin’s comprehensive benefits package here. Further Information About This Opportunity: This position is a full-time remote (telework) role. Citizenship / Clearance: MUST BE A U.S. CITIZEN – This position is located at a facility that requires special access. A Secret clearance is required for this role but is not required to start (the selected candidate must be able to obtain a Secret clearance). Basic Qualifications • Associate degree or higher in Electrical Engineering, Electronics Technology, Microelectronics, or a related technical discipline (Bachelor's degree strongly preferred), or equivalent experience • Minimum 12 years of experience in full-custom analog or mixed-signal IC layout design (or 10+ years with a Bachelor's degree in a related field) • Expert-level proficiency with Synopsys Custom Compiler (or Custom Designer) and the Cadence Virtuoso layout environment • Experience driving physical-verification closure (DRC, LVS, ERC, ANT) to sign-off across multiple foundry processes • Layout experience across process nodes including BCD technologies • Must be a US Citizen; must possess or be able to obtain a DoD Secret clearance Desired Skills • Demonstrated experience as the physical-design / layout technical lead on a major effort, with responsibility for floorplan through tape-out of complex analog and mixed-signal ICs • Layout experience across process nodes ranging from 130 nm to 12 nm • Bachelor degree or higher in Electrical Engineering, Microelectronics, or a related field; Master's degree or PhD preferred • EMIR analysis experience, including IR-drop and electromigration mitigation at the program level • Advanced layout automation and scripting skills (SKILL, Tcl, Python, or Perl) with a track record of deploying reusable methodology across a department • Layout experience with precision analog blocks such as PLLs, ADC/DACs, LDOs, bandgap references, or amplifiers • Experience developing and maintaining layout methodology, design-rule decks, and best-practice guidelines across multiple foundries • Experience owning tape-out sign-off packages and chairing physical-design review gates on concurrent programs • Demonstrated ability to lead technical teams, mentor staff engineers, and influence physical-design direction across organizational boundaries • Excellent verbal and written communication skills with demonstrated ability to brief leadership, customers, and non-technical audiences • Strong mentoring track record with mid-career and staff-level layout engineers • Successful proposal/capture contribution experience (BOE, technical-volume authoring, technical strategy) on major IC programs • Previous experience related to aerospace/defense IC design techniques • Prior experience with Lockheed Martin MFC • Active DoD Secret or Top Secret clearance Pay Information GeoZone Definition: GeoZones are geographic groupings created by Lockheed Martin to align compensation ranges with regional labor markets and cost-of-labor differences across the United States. Locations are assigned a Geo Zone based on the primary work location of the role. • Full-time salary range (GEOZONE 1): $185400.00 - $344400.00 • Includes metropolitan areas such as Sunnyvale CA; Pal Alto, CA; New York City metropolitan area; Newark, New Jersey; etc. • Full-time salary range (GEOZONE 2): $166900.00 - $309900.00 • Includes metropolitan areas such as Denver, CO; King of Prussia, PA; Stratford, CT; Moorestown, NJ; etc. • Full-time salary range (GEOZONE 3): $148300.00 - $275500.00 • Includes metropolitan areas such as Dallas–Fort Worth, TX; Orlando, FL; Grand Prairie, TX; Marietta, GA; etc. • Full-time salary range (GEOZONE 4): $133500.00 - $247900.00 • Includes metropolitan areas such as Camden, AR; Lexington, KY; Lufkin, TX; etc. At Lockheed Martin, we know mission success starts with taking care of our people. Our Total Rewards program is designed to attract top talent, support your well-being, and help you grow—both professionally and personally. The salary range for this position is as listed on the requisition. Please note that the salary information listed is a general guideline only. Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market(work location) and business considerations when extending an offer. Benefits offered: Medical, Dental, Vision, Flexible work arrangements and schedules (e.g., 4x10), 401(k) match, Paid time off, Holidays, Parental Leave, EAP, Flexible Spending Accounts, Education Assistance, Life Insurance, Short-Term Disability, and Long-Term Disability. • Annual short-term and/or long-term incentive compensation programs may be offered depending on the position. Payments under these annual programs are not guaranteed and can vary from year to year and are tied to a range of performance metrics. • For (Washington state applicants only) Non-represented full-time employees: accrue at least 10 hours per month of Paid Time Off (PTO) to be used for incidental absences and other reasons; receive at least 90 hours for holidays. Represented full time employees accrue 6.67 hours of Vacation per month; accrue up to 52 hours of sick leave annually; receive at least 96 hours for holidays. PTO, Vacation, sick leave, and holiday hours are prorated based on start date during the calendar year.

Requirements

Must-haves

Standard Job Description
What You Will Be Doing
Leading full-custom analog and mixed-signal layout across multiple programs, from floorplan through place-and-route of analog blocks, optimizing area, device matching, signal integrity, and power delivery
Owning the physical-design technical strategy for device generations from 130 nm to 12 nm, including high-voltage BCD processes, and driving layout methodology standardization across the department
This position is a full-time remote (telework) role.
Minimum 12 years of experience in full-custom analog or mixed-signal IC layout design (or 10+ years with a Bachelor's degree in a related field)
Expert-level proficiency with Synopsys Custom Compiler (or Custom Designer) and the Cadence Virtuoso layout environment
Experience driving physical-verification closure (DRC, LVS, ERC, ANT) to sign-off across multiple foundry processes
Layout experience across process nodes including BCD technologies
Must be a US Citizen; must possess or be able to obtain a DoD Secret clearance

Nice-to-haves

Associate degree or higher in Electrical Engineering, Electronics Technology, Microelectronics, or a related technical discipline (Bachelor's degree strongly preferred), or equivalent experience
Demonstrated experience as the physical-design / layout technical lead on a major effort, with responsibility for floorplan through tape-out of complex analog and mixed-signal ICs
Layout experience across process nodes ranging from 130 nm to 12 nm
Bachelor degree or higher in Electrical Engineering, Microelectronics, or a related field; Master's degree or PhD preferred
EMIR analysis experience, including IR-drop and electromigration mitigation at the program level
Advanced layout automation and scripting skills (SKILL, Tcl, Python, or Perl) with a track record of deploying reusable methodology across a department
Layout experience with precision analog blocks such as PLLs, ADC/DACs, LDOs, bandgap references, or amplifiers
Experience developing and maintaining layout methodology, design-rule decks, and best-practice guidelines across multiple foundries
Experience owning tape-out sign-off packages and chairing physical-design review gates on concurrent programs
Demonstrated ability to lead technical teams, mentor staff engineers, and influence physical-design direction across organizational boundaries
Excellent verbal and written communication skills with demonstrated ability to brief leadership, customers, and non-technical audiences
Strong mentoring track record with mid-career and staff-level layout engineers

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Benefits

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Dental

Vision

401(K)

Pto

Paid Time Off

Parental Leave