Job description

About Etched Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning. ASIC Timing Engineer Etched is seeking an exceptional ASIC Timing Engineer to join our innovative team. The candidate will be responsible for driving timing analysis and closure of our next-generation AI chips, ensuring that we meet the high-performance demands of our unique architecture. Representative Projects: Drive timing analysis and closure of chips at block, cluster, and full chip level Collaborate with Physical Design, DFX, Clocks, and other teams to develop timing closure strategies, create timing constraints, and ensure timing and power convergence, as well as ECO implementation Enhance timing convergence flows in partnership with our methodology teams Contribute to DFT logic understanding and assist with DFT timing closure for various modes, such as scan and BIST Work on timing closure of digital logic/macros in AMS designs/IPs, ensuring all aspects are addressed You maybe a good fit if you have: BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years of experience, or MS (or equivalent experience) with 2+ years of experience in Timing and STA Hands-on experience in full-chip/sub-chip Static Timing Analysis(STA)/Fishtail, Lint, CDC, RDC checks, and timing convergence, including timing constraints generation and management Expertise in analyzing and fixing timing paths through ECOs, with a focus on crosstalk and noise analysis In-depth knowledge of RTL to Netlist, industry-standard STA and timing convergence tools Familiarity with deep sub-micron process nodes, including modeling and converging timing in these nodes Background in domain-specific STA and timing convergence, particularly with GPUs, CPUs, DPUs/Network processors, or SoCs Experience in methodology and/or flow development, as well as automation We encourage you to apply even if you do not believe you meet every single qualification. How we’re different: Etched believes in the Bitter Lesson . We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed. Benefits: Full medical, dental, and vision packages, with 100% of premium covered, 90% for dependents Housing subsidy of $2,000/month for those living within walking distance of the office Daily lunch and dinner in our office Relocation support for those moving to Cupertino

Requirements

Must-haves

Drive timing analysis and closure of chips at block, cluster, and full chip level
Collaborate with Physical Design, DFX, Clocks, and other teams to develop timing closure strategies, create timing constraints, and ensure timing and power convergence, as well as ECO implementation
Enhance timing convergence flows in partnership with our methodology teams
Contribute to DFT logic understanding and assist with DFT timing closure for various modes, such as scan and BIST
Work on timing closure of digital logic/macros in AMS designs/IPs, ensuring all aspects are addressed
You maybe a good fit if you have:
BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years of experience, or MS (or equivalent experience) with 2+ years of experience in Timing and STA
Hands-on experience in full-chip/sub-chip Static Timing Analysis(STA)/Fishtail, Lint, CDC, RDC checks, and timing convergence, including timing constraints generation and management
Expertise in analyzing and fixing timing paths through ECOs, with a focus on crosstalk and noise analysis
In-depth knowledge of RTL to Netlist, industry-standard STA and timing convergence tools
Familiarity with deep sub-micron process nodes, including modeling and converging timing in these nodes
Background in domain-specific STA and timing convergence, particularly with GPUs, CPUs, DPUs/Network processors, or SoCs
Experience in methodology and/or flow development, as well as automation
We encourage you to apply even if you do not believe you meet every single qualification.
We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

Nice-to-haves

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Platform: greenhouse
Effort: quick

Benefits

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Dental

Vision