Job description

As part of the Pixel IP ANE design and integration engineer in pixel IP team, you will work closely with different cross functional team, including architecture, verification, power, physical design and more. Extensive knowledge of computer architecture is required, including bus topologies and protocols, such as AMBA. This role includes the following tasks: - Doing RTL design on high speed, high performance subsystem. - Working with design verification and formal verification teams to fully verify design and performance - Working with physical design and static timing team to produce high quality netlist through synthesis. - Analyze clock domain crossing design for correctness - Working with DFT, and BIST team to ensure design can be fully tested. BS + 10 years of experience Extensive knowledge of bus topology, such as AMBA Experience working on large, high speed, compute system Good knowledge base on Clock Domain Crossing designs Experience with Synthesis Experience with Static Timing Analysis Experience working with Power Intent

Requirements

Must-haves

Doing RTL design on high speed, high performance subsystem.
Working with design verification and formal verification teams to fully verify design and performance
Working with physical design and static timing team to produce high quality netlist through synthesis.
Analyze clock domain crossing design for correctness
Working with DFT, and BIST team to ensure design can be fully tested.
BS + 10 years of experience
Extensive knowledge of bus topology, such as AMBA
Experience working on large, high speed, compute system
Good knowledge base on Clock Domain Crossing designs
Experience with Synthesis
Experience with Static Timing Analysis
Experience working with Power Intent

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: apple
Effort: medium