Job description

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Principal Subsystem Design Manager to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Artificial Intelligence System on Chip (AISoC) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Principal Subsystem Design Manager with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal Subsystem Design Manager to join the team. Responsibilities The AISoC silicon team is seeking a Principal Subsystem Design Manager to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom Intellectual Property (IP) and System on Chip (SoC) designs that can perform complex and high-performance functions in an extremely efficient manner.  • Build, hire, and mentor a team of engineers, supporting their career growth and professional development. • Manage a Subsystem design team with focus on architectural and micro-architectural based functions and features. • Technically lead one or more Subsystems. • Interact with architects to develop micro-architectural specifications and work with DV engineers to execute them. • Collaborate across teams on vertical and horizontal reuse of components. • Apply Agile development methodologies including code reviews, sprint planning, and feature deployment. • Provide technical leadership through mentorship and collaboration. Qualifications Required Qualifications: • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Equivalent Experience. Other Requirements: • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Preferred Qualifications: • 9+ years of related technical engineering experience • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience. • 8+ years expertise in digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, and CDC/Lint closure. • 8+ years of experience in synthesis, timing constraints, power / performance / area (PPA) trade-offs and post-silicon debug. • 15+ years of relevant experience. • 7+ years experience with lead roles across cross-functional / cross-time-zone engineering teams. • Lead experience for an IP or SS related to CPUs, VPUs, GPUs, Direct Memory Access (DMA) engine, Tensor unit, or similar • Experience of working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs  • Experience in Scripting language such as Python or Perl. • Experience with design quality and static checks, DFT implementation and hand off to physical design. #SCHIE Silicon Engineering M5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: careers.microsoft.com This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Requirements

Must-haves

We are looking for a Principal Subsystem Design Manager to join the team.
Build, hire, and mentor a team of engineers, supporting their career growth and professional development.
Manage a Subsystem design team with focus on architectural and micro-architectural based functions and features.
Technically lead one or more Subsystems.
Interact with architects to develop micro-architectural specifications and work with DV engineers to execute them.
Collaborate across teams on vertical and horizontal reuse of components.
Apply Agile development methodologies including code reviews, sprint planning, and feature deployment.
Provide technical leadership through mentorship and collaboration.
OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
8+ years expertise in digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, and CDC/Lint closure.
8+ years of experience in synthesis, timing constraints, power / performance / area (PPA) trade-offs and post-silicon debug.
15+ years of relevant experience.
7+ years experience with lead roles across cross-functional / cross-time-zone engineering teams.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Nice-to-haves

Lead experience for an IP or SS related to CPUs, VPUs, GPUs, Direct Memory Access (DMA) engine, Tensor unit, or similar
Experience of working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs
Experience in Scripting language such as Python or Perl.
Experience with design quality and static checks, DFT implementation and hand off to physical design.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

azureagileaimachine learningmlpython

Platform: eightfold
Effort: medium

Benefits

Benefits detected in the listing.

Vision

Professional Development