Job description

NVIDIA’s Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first-principles thinking and engineering judgment at the highest level translate directly into product outcomes at scale. Our team gets every GPU, SoC, and CPU silicon program from first power-on to high-volume production! We are hiring a Senior Silicon Product Engineer – Manufacturing to join our Testability, Manufacturability, Reliability & Quality (TMRQ) team. In this role, you will co-design and implement SLT Production diagnostics for silicon features in a high-volume manufacturing environment, verify POR specifications, and support post-silicon validation for some of the industry’s most complex semiconductor chips. You should have experience defining and validating SLT production coverage specifications on silicon and translating product requirements into effective test coverage that delivers quality, yield, and efficiency at scale. Hands-on lab experience with system-level post-silicon bring-up and silicon debugging is required. This role sits at the intersection of multi-functional HW/SW teams and Production Operations to make manufacturing an outstanding part of the overall Silicon co-design cycle, production release, and HVM testing! The exceptional hire continuously improves high-volume manufacturing workflows and products multi-functionally and uses AI deliberately to drive impact while managing risk. What you will be doing: • Partner multi-functionally with HW engineering teams such as Silicon PVT design and characterization teams, IO design and validation teams, system feature owners, SLT and BLT Production Operations, etc., to determine test coverage and constraints to resolve appropriate SLT test conditions, test content, and flows for high-volume manufacturing screens. • Partner with SW and platform teams to support and improve SLT testing infrastructure, debug knobs, and data collection features needed to support manufacturing screens effectively. • Co-design SLT testability scope and coverage enhancements for Nvidia's manufacturing testing with a focus on high-volume system-level manufacturing screens. • Prototype and fine-tune speed, power, circuits, yield, and quality for effective silicon coverage in the SLT socketed environment. • Co-design, develop, and maintain SLT testing flows and incorporate takeaways from silicon and correlate to design. • Define procedures to facilitate Silicon correlation activities between production testing infrastructure and internal Si characterization and diagnostics programs. • Support customer-facing and quality teams during customer escalations to understand the issues and fix gaps identified in SLT production coverage. • Drive alignment for manufacturability, test time optimization and reduction, cost vs. coverage tradeoffs, etc., to evaluate the effectiveness of new tests. • Initiate and drive process improvements and preventative actions through root cause analysis and data analytics. What we need to see: • Bachelor’s or Master’s Degree or equivalent in Microelectronics/Electrical/Electronic/Computer Engineering or equivalent experience. • 8+ years of relevant proven experience in silicon Post-silicon PVT validation and/or High-volume manufacturing testing for sophisticated SoCs, GPUs, CPUs, or similar. • Hands-on lab experience with silicon bring-up, lab debug, test content bring-up, and correlation to Si characterization, yield, and coverage optimization. • Strong EE fundamentals, device physics, knowledgeable in Silicon design, statistics, STA concepts, signal integrity, fault analysis, sampling, and computer architecture. • Excellent interpersonal skills and demonstrated ability to drive multi-functional alignment around plans, dependencies, and sign-off criteria. • Prior ownership of manufacturing test strategy for a major silicon product (e.g., GPU/SoC/CPU) from early planning through ramp to QS/production. • Strong data analysis skills. Prior experience working with volume data is a plus. • Good understanding of firmware/driver structures and their interaction with HW. • Problem-solving, debugging, analysis, and logical reasoning skills with examples to prove it. • Experience with Python, BASH, Linux, and scripting. Ways to stand out above the crowd: • Outstanding work ethic and up-leveling discussions to solve the real problems • Native use of AI tools to accelerate production testing and debug workflows • Battle-tested on GPUs, CPUs, AI accelerators, or other large-scale SoCs — you’ve seen firsthand how complexity at scale reshapes the failure landscape and demands a different level of engineering intuition. • Co-designed or led multi-functional alignment on production methodologies adopted by other teams in a High Volume Manufacturing(HVM) environment. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits . Applications for this job will be accepted at least until October 20, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Requirements

Must-haves

Partner with SW and platform teams to support and improve SLT testing infrastructure, debug knobs, and data collection features needed to support manufacturing screens effectively.
Co-design SLT testability scope and coverage enhancements for Nvidia's manufacturing testing with a focus on high-volume system-level manufacturing screens.
Prototype and fine-tune speed, power, circuits, yield, and quality for effective silicon coverage in the SLT socketed environment.
Co-design, develop, and maintain SLT testing flows and incorporate takeaways from silicon and correlate to design.
Define procedures to facilitate Silicon correlation activities between production testing infrastructure and internal Si characterization and diagnostics programs.
Support customer-facing and quality teams during customer escalations to understand the issues and fix gaps identified in SLT production coverage.
Drive alignment for manufacturability, test time optimization and reduction, cost vs. coverage tradeoffs, etc., to evaluate the effectiveness of new tests.
Initiate and drive process improvements and preventative actions through root cause analysis and data analytics.
Bachelor’s or Master’s Degree or equivalent in Microelectronics/Electrical/Electronic/Computer Engineering or equivalent experience.
8+ years of relevant proven experience in silicon Post-silicon PVT validation and/or High-volume manufacturing testing for sophisticated SoCs, GPUs, CPUs, or similar.
Hands-on lab experience with silicon bring-up, lab debug, test content bring-up, and correlation to Si characterization, yield, and coverage optimization.
Strong EE fundamentals, device physics, knowledgeable in Silicon design, statistics, STA concepts, signal integrity, fault analysis, sampling, and computer architecture.
Excellent interpersonal skills and demonstrated ability to drive multi-functional alignment around plans, dependencies, and sign-off criteria.
Prior ownership of manufacturing test strategy for a major silicon product (e.g., GPU/SoC/CPU) from early planning through ramp to QS/production.
Good understanding of firmware/driver structures and their interaction with HW.
Problem-solving, debugging, analysis, and logical reasoning skills with examples to prove it.
Experience with Python, BASH, Linux, and scripting.
Outstanding work ethic and up-leveling discussions to solve the real problems
Native use of AI tools to accelerate production testing and debug workflows
Battle-tested on GPUs, CPUs, AI accelerators, or other large-scale SoCs — you’ve seen firsthand how complexity at scale reshapes the failure landscape and demands a different level of engineering intuition.
Co-designed or led multi-functional alignment on production methodologies adopted by other teams in a High Volume Manufacturing(HVM) environment.
You will also be eligible for equity and benefits .
Applications for this job will be accepted at least until October 20, 2026.

Nice-to-haves

Strong data analysis skills. Prior experience working with volume data is a plus.

Application prep

Use the role’s language and application details while tailoring your materials.

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