Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: We are seeking an exceptional SoC Architect to lead the architecture definition and technical direction of our next‑generation SoCs deployed across a wide range of applications including AI, Data Center, Security, Communications, and Embedded Computing . This individual will define the overall SoC architecture, drive system‑level innovation, and deliver breakthrough architectures spanning heterogeneous compute, advanced memory systems, leading‑edge I/Os, high‑performance interconnects, and AI/Networking/Storage/Compute/Crypto acceleration. As a senior technical leader, you will influence long‑term silicon architecture strategy, collaborate closely with internal/external partners, and guide teams across architecture, design, verification, physical implementation, software, and customer engineering. This role has broad organizational impact and is integral to shaping the future of AMD’s Adaptive, Embedded, and Custom SoCs. THE PERSON: You are a recognized industry expert in heterogeneous SoC architecture, with deep experience in CPUs, AI/Networking/Storage/Compute/Crypto acceleration, advanced protocols such as PCIe, UCIe, UAL and/or Ethernet, and high‑bandwidth memory/interconnect design. You have demonstrated leadership experience on complex technical programs, balancing performance, power, area, and cost tradeoffs. You communicate with authority and empathy, and thrive in fast‑paced, cross‑domain environments.You bring a strong innovation mindset, a passion for leadership on complex and technically challenging programs, and a track record of delivering differentiated SoC solutions. KEY RESPONSIBILITIES: • Own and lead the architecture of next‑gen SoCs, spanning high performance multi-processor subsystems, coherent and non‑coherent interconnects, memory and cache hierarchies, advanced I/O, and AI, Networking, Storage, Compute and Crypto acceleration. • Define long‑term SoC architectural strategy aligned with product, roadmap, and customer requirements. • Develop clear, detailed SoC architecture specifications covering compute, memory, accelerators, on-chip and off-chip interconnect, RAS, security, boot/configuration, and SoC management subsystems. • Guide cross‑functional execution, providing leadership across RTL design, verification, physical design, firmware, software, and platform teams. • Collaborate deeply with leading-edge AI, Data Center, Security, Communications, and Embedded Computing customers, translating RFQs and use-cases into robust SoC architectural requirements. • Evaluate emerging processor IP, including next‑gen x86/ARM/RISC-V cores, compute accelerators, and next generation PCIe, CXL, Ethernet, DDR, UCIe, and/or UAL protocols . • Lead PPA trade‑off decisions, ensuring architectural choices align with product cost, performance, power targets, and manufacturability constraints. • Innovate cross‑domain technologies such as hardware security, heterogeneous coherency, traffic shaping, system QoS, and power management. • Mentor architects across the organization, elevating architectural rigor, methodology, and technical leadership capability. • Create flexible and modular subsystem architectures that can be deployed in either chiplet, monolithic or 3D form factors. • Author architecture specifications in clear and concise language. Guide and assist pre-silicon design/verification and post-silicon validation during the execution phase. PREFERRED EXPERIENCE: • Proven track record defining and delivering architecture for complex heterogeneous SoCs in advanced nodes. • Expertise in x86, ARM or RISC-V based processor subsystems and heterogeneous acceleration. • Deep technical knowledge of the PCIe, CXL, Ethernet, DDR, UCIe, and UAL protocol specifications, and how their mandatory and optional protocol features are leveraged in the SoC or system. • Strong technical leadership across interconnect fabrics, memory and I/O technology & sub subsystems. • Familiarity with high‑speed I/O protocols, multi‑chiplet partitioning, and chiplet interconnect standards. • Proficiency with architectural modeling and performance simulation frameworks. • Demonstrated ability to influence silicon strategy, ecosystem partners, and customer roadmaps. ACADEMIC CREDENTIALS: • MS or PhD in Electrical/Computer Engineering, or related field. • Technical expert and thought leader in SoC Architecture, with patents, publications, or major architectural wins strongly preferred. LOCATION: San Jose, CA or Austin, TX #LI-MH2 Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Requirements

Must-haves

ADVANCE YOUR CAREER. ADVANCE THE WORLD.
Define long‑term SoC architectural strategy aligned with product, roadmap, and customer requirements.
Develop clear, detailed SoC architecture specifications covering compute, memory, accelerators, on-chip and off-chip interconnect, RAS, security, boot/configuration, and SoC management subsystems.
Guide cross‑functional execution, providing leadership across RTL design, verification, physical design, firmware, software, and platform teams.
Collaborate deeply with leading-edge AI, Data Center, Security, Communications, and Embedded Computing customers, translating RFQs and use-cases into robust SoC architectural requirements.
Evaluate emerging processor IP, including next‑gen x86/ARM/RISC-V cores, compute accelerators, and next generation PCIe, CXL, Ethernet, DDR, UCIe, and/or UAL protocols .
Lead PPA trade‑off decisions, ensuring architectural choices align with product cost, performance, power targets, and manufacturability constraints.
Innovate cross‑domain technologies such as hardware security, heterogeneous coherency, traffic shaping, system QoS, and power management.
Mentor architects across the organization, elevating architectural rigor, methodology, and technical leadership capability.
Create flexible and modular subsystem architectures that can be deployed in either chiplet, monolithic or 3D form factors.
Author architecture specifications in clear and concise language. Guide and assist pre-silicon design/verification and post-silicon validation during the execution phase.
MS or PhD in Electrical/Computer Engineering, or related field.
LOCATION: San Jose, CA or Austin, TX
Benefits offered are described: AMD benefits at a glance .
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.

Nice-to-haves

Proven track record defining and delivering architecture for complex heterogeneous SoCs in advanced nodes.
Expertise in x86, ARM or RISC-V based processor subsystems and heterogeneous acceleration.
Deep technical knowledge of the PCIe, CXL, Ethernet, DDR, UCIe, and UAL protocol specifications, and how their mandatory and optional protocol features are leveraged in the SoC or system.
Strong technical leadership across interconnect fabrics, memory and I/O technology & sub subsystems.
Familiarity with high‑speed I/O protocols, multi‑chiplet partitioning, and chiplet interconnect standards.
Proficiency with architectural modeling and performance simulation frameworks.
Demonstrated ability to influence silicon strategy, ecosystem partners, and customer roadmaps.
Technical expert and thought leader in SoC Architecture, with patents, publications, or major architectural wins strongly preferred.

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Platform: amd
Effort: medium

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