AI SoC Architect Networking at Majestic Labs

Job description

Description We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About the position This is a highly technical and cross-functional role requiring deep expertise in SoC networking, high-speed interconnects, and protocol acceleration for AI. As a SOC System Network Architect for AI, you will lead the definition and architectural design of network engines and interconnect fabrics powering our custom AI servers. You will collaborate closely with silicon architecture, hardware design, firmware, and software teams to shape scale-up and scale-out networking topologies optimized for distributed AI workloads. Responsibilities • Architect end-to-end SoC networking engines, SmartNIC/NIC architectures, and switch interface IPs for AI accelerators • Define scale-up (intra-node) and scale-out (inter-node) network topologies • Design hardware acceleration and offload engines for AI collective operations (e.g., AllReduce, AllGather, AllToAll) directly on the network fabric • Optimize transport protocols (RoCEv2, custom RDMA engines, TCP/UDP offloads) and adaptive routing/congestion control algorithms (e.g., DCQCN) for synchronized AI traffic flows • Drive performance modeling, cycle-accurate simulations, and traffic pattern analysis to evaluate architectural trade-offs across network fabrics • Collaborate with ASIC design, silicon architecture, and AI software teams to define hardware/software interfaces, register abstractions, and programming models • Produce high-quality network architecture specifications, interface documents, and lead cross-functional architecture reviews Requirements • 7+ years of hands-on network architecture, SoC interconnect design, or silicon engineering experience, with at least 3 years in an architecture or technical lead capacity • B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or Computer Science • Proven track record of owning and delivering complex network ASICs, NIC engines, or switch architectures from initial concept through silicon bring-up Core Technical Skills • Deep expertise in SmartNIC/NIC architecture, RDMA technologies (RoCEv2, InfiniBand), and hardware transport protocol engines • Strong understanding of scale-up and scale-out topologies, high-speed packet processing, and switch architecture trade-offs • In-depth knowledge of AI communication patterns and hardware acceleration for network collective operations • Solid foundation in lower-level network protocols (TCP/UDP, Ethernet, IP) and advanced network congestion control mechanisms • Proficiency in network performance modeling, hardware simulation tools, and architectural trade-off analysis Preferred Qualifications • Experience with high-speed proprietary interconnects (e.g., NVLink, NVSwitch, UALink, CXL) or custom switch silicon • Hands-on experience with network simulation and modeling frameworks (e.g., ns-3, OMNeT++, SystemC/TLM) • Familiarity with distributed AI communication libraries (e.g., NCCL, RCCL) and frameworks (PyTorch, DeepSpeed) We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability, we want to meet you!

Requirements

Must-haves

Architect end-to-end SoC networking engines, SmartNIC/NIC architectures, and switch interface IPs for AI accelerators
Define scale-up (intra-node) and scale-out (inter-node) network topologies
Design hardware acceleration and offload engines for AI collective operations (e.g., AllReduce, AllGather, AllToAll) directly on the network fabric
Optimize transport protocols (RoCEv2, custom RDMA engines, TCP/UDP offloads) and adaptive routing/congestion control algorithms (e.g., DCQCN) for synchronized AI traffic flows
Drive performance modeling, cycle-accurate simulations, and traffic pattern analysis to evaluate architectural trade-offs across network fabrics
Collaborate with ASIC design, silicon architecture, and AI software teams to define hardware/software interfaces, register abstractions, and programming models
Produce high-quality network architecture specifications, interface documents, and lead cross-functional architecture reviews
7+ years of hands-on network architecture, SoC interconnect design, or silicon engineering experience, with at least 3 years in an architecture or technical lead capacity
B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or Computer Science
Proven track record of owning and delivering complex network ASICs, NIC engines, or switch architectures from initial concept through silicon bring-up
Core Technical Skills
Deep expertise in SmartNIC/NIC architecture, RDMA technologies (RoCEv2, InfiniBand), and hardware transport protocol engines
Strong understanding of scale-up and scale-out topologies, high-speed packet processing, and switch architecture trade-offs
In-depth knowledge of AI communication patterns and hardware acceleration for network collective operations
Solid foundation in lower-level network protocols (TCP/UDP, Ethernet, IP) and advanced network congestion control mechanisms
Proficiency in network performance modeling, hardware simulation tools, and architectural trade-off analysis

Nice-to-haves

Experience with high-speed proprietary interconnects (e.g., NVLink, NVSwitch, UALink, CXL) or custom switch silicon
Hands-on experience with network simulation and modeling frameworks (e.g., ns-3, OMNeT++, SystemC/TLM)
Familiarity with distributed AI communication libraries (e.g., NCCL, RCCL) and frameworks (PyTorch, DeepSpeed)

Application prep

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Platform: comeet
Effort: medium