Hardware Physical Design Engineer # 26-26068

• Duration: 6 months contract
• This is a Physical Design Engineering role that will require taking the design from RTL to GDS with synthesis, Place n Route, timing, and Physical Verification.
• Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams.
• This engineer will work on high-speed multi-gigabit SerDes PHY designs.
• This includes timing driven place and route of RTL blocks for high speed Datapath and control logic applications.
• Design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
• You will also support floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.
• 2-5+ years working experience.
• Strong background in digital circuit techniques, efficient and robust implementation topologies for logic functions, logic optimization, and transistor level circuit topologies for high speed, low power applications.
• Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.
• Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation.
• Major in EE, CS or related, master’s degree preferably with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs.

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