Job description

Duration: 11 months Schedule:Day-1 Onsite Job Description: • You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. • Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. • You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. • As part of this team, you’ll contribute to developing next-generation networking chips. Responsibilities: • Being a member of the design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. • Option to also do block level RTL design or block or top-level IP integration. • Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level. • Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle. • Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development. • Creating fullchip clocking diagrams and related documentation. Experience: • 8 Years of experience Skillsets: • Experience with block/full chip SDC development in functional and test modes. • Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus. • Understanding of related digital design concepts (e.g., clocking and async boundaries). • Experience with synthesis tools (e.g., Synopsys DC/DCG/FC), Verilog/System Verilog programming. • Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence). • Experience with Spyglass CDC and glitch analysis. • Experience using Formal Verification: Synopsys Formality and Cadence LEC. • Experience with scripting languages such as Python, Perl, or TCL. Education: • Bachelor’s Degree in Electrical or Computer Engineering with 7 years of ASIC or related experience or Master’s Degree in Electrical or Computer Engineering with 5 years of ASIC or related experience. US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit www.ustechsolutions.com . US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. AI Statement: By applying, you acknowledge that AI-assisted tools may be used during hiring. #LI-AS140

Requirements

Must-haves

Duration: 11 months
Schedule:Day-1 Onsite
You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity.
Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels.
You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure.
As part of this team, you’ll contribute to developing next-generation networking chips.
Being a member of the design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
Option to also do block level RTL design or block or top-level IP integration.
Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
Creating fullchip clocking diagrams and related documentation.
8 Years of experience
Experience with block/full chip SDC development in functional and test modes.
Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus.
Understanding of related digital design concepts (e.g., clocking and async boundaries).
Experience with synthesis tools (e.g., Synopsys DC/DCG/FC), Verilog/System Verilog programming.
Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence).
Experience with Spyglass CDC and glitch analysis.
Experience using Formal Verification: Synopsys Formality and Cadence LEC.
Experience with scripting languages such as Python, Perl, or TCL.
Bachelor’s Degree in Electrical or Computer Engineering with 7 years of ASIC or related experience or Master’s Degree in Electrical or Computer Engineering with 5 years of ASIC or related experience.
US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit www.ustechsolutions.com .
AI Statement: By applying, you acknowledge that AI-assisted tools may be used during hiring.

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