Job description

We are now looking for a Senior Circuit Timing Engineer! NVIDIA stands at the intersection of hardware excellence and AI breakthrough, where every line of code and every chip design ripples across industries worldwide. We've built the computational backbone for autonomous systems, revolutionized data center architecture, and created the silicon that powers the AI revolution. Our resilience through decades of technological shifts has forged a unique engineering culture—one where ambitious projects meet exceptional talent. From deep learning frameworks to cutting-edge robotics, we're not just participants in the fourth industrial revolution; we're its architects. Discover how your engineering vision can reshape the world alongside ours. What you'll be doing: • Participate in ground breaking processor design in deep submicron technologies. • Work as part of a global circuits team to design innovative circuits for hardware security, adaptive clocking, and power management solutions. • Drive timing analysis and signoff of custom circuit macros (digital, semi-custom and analog mixed-signal). • Validate timing of custom circuit designs using STA tools including Nanotime, PrimeTime, Tempus and various SPICE simulation tools. • Collaborate with cross-functional teams to improve the power, performance, area and reliability of NVIDIA's next generation products through custom circuit solutions and detailed transistor-level analysis. • Develop timing models and methodology for innovative and unique custom macro designs. • Transistor-level circuit design and timing, schematic entry, and layout delivery. • Integrate AI/ML techniques directly into the design process and methodology. • Work with PD, DFX, Clocks, and other teams on timing signoff strategy, timing constraints, timing and power convergence, DFT, as well as timing ECO implementation. What we need to see: • BSEE/MS preferred in Electrical, Computer Engineering or equivalent experience. • 6+ years of digital circuit design experience for Masters and 8+ years for Bachelors. • Excellent understanding of deep submicron process issues and digital circuit design techniques is required. • Expertise and in-depth knowledge of industry standard STA tools such as Nanotime, Primetime, Tempus, and other timing analysis tools. • Hands on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure is required. • Proven experience in timing constraints generation and management. • Hands on experience in design and analysis of low power circuits (power gating, decaps, multi-vt, etc..) is a plus. • Expertise in analysis and fixing of timing paths through ECOs including crosstalk and glitch noise. • Solid understanding of extracted timing models and the usage of .libs in Primetime. • Knowledge of process variation effect modeling and experience in design convergence in multi GHz deep submicron technology. Ways to stand out from the crowd: • Proven ownership and hands-on experience across the entire silicon design flow, from micro-architecture and RTL design to back-end execution, including Custom/Semi-Custom Circuit Design, Synthesis, Auto Place and Route, STA, and PVerf. • Proven capability in Post-Silicon characterization and debug, ensuring designs meet performance targets in hardware. • Track record of independently driving and delivering complex features from conception through tape-out and validation. • Knowledge of timing closure strategies for digital logic/macros part of AMS designs/IPs. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits . Applications for this job will be accepted at least until October 15, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Requirements

Must-haves

We are now looking for a Senior Circuit Timing Engineer!
Participate in ground breaking processor design in deep submicron technologies.
Work as part of a global circuits team to design innovative circuits for hardware security, adaptive clocking, and power management solutions.
Drive timing analysis and signoff of custom circuit macros (digital, semi-custom and analog mixed-signal).
Validate timing of custom circuit designs using STA tools including Nanotime, PrimeTime, Tempus and various SPICE simulation tools.
Collaborate with cross-functional teams to improve the power, performance, area and reliability of NVIDIA's next generation products through custom circuit solutions and detailed transistor-level analysis.
Develop timing models and methodology for innovative and unique custom macro designs.
Transistor-level circuit design and timing, schematic entry, and layout delivery.
Integrate AI/ML techniques directly into the design process and methodology.
Work with PD, DFX, Clocks, and other teams on timing signoff strategy, timing constraints, timing and power convergence, DFT, as well as timing ECO implementation.
6+ years of digital circuit design experience for Masters and 8+ years for Bachelors.
Excellent understanding of deep submicron process issues and digital circuit design techniques is required.
Expertise and in-depth knowledge of industry standard STA tools such as Nanotime, Primetime, Tempus, and other timing analysis tools.
Hands on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure is required.
Proven experience in timing constraints generation and management.
Expertise in analysis and fixing of timing paths through ECOs including crosstalk and glitch noise.
Solid understanding of extracted timing models and the usage of .libs in Primetime.
Knowledge of process variation effect modeling and experience in design convergence in multi GHz deep submicron technology.
Proven capability in Post-Silicon characterization and debug, ensuring designs meet performance targets in hardware.
Track record of independently driving and delivering complex features from conception through tape-out and validation.
Knowledge of timing closure strategies for digital logic/macros part of AMS designs/IPs.
You will also be eligible for equity and benefits .

Nice-to-haves

BSEE/MS preferred in Electrical, Computer Engineering or equivalent experience.
Hands on experience in design and analysis of low power circuits (power gating, decaps, multi-vt, etc..) is a plus.

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aiml

Platform: eightfold
Effort: medium

Benefits

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