Job description

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life. We are seeking an FPGA/VLSI engineer to contribute to digital hardware development targeting ASIC/SoC platforms used in advanced communication systems. This role focuses on RTL design, FPGA prototyping, and system integration, working closely with cross-functional teams to deliver high-quality designs. Responsibilities: • Design and implement RTL using SystemVerilog with consideration for timing, power, and area • Perform FPGA prototyping, validation, and hardware bring-up for digital designs • Develop and execute simulation and debugging strategies at block and subsystem levels • Contribute to SoC-level integration, including interfacing with processors, memory, and peripherals • Analyze and resolve timing issues, including setup/hold violations and basic clock domain crossing concerns • Collaborate with verification, ASIC, and software teams to ensure functional correctness and performance • Participate in design reviews and contribute to improving design quality and best practices Qualifications: • Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field • Strong experience writing synthesizable SystemVerilog/Verilog • Proven experience with FPGA development flows, including synthesis, implementation, and validation • Solid understanding of digital design fundamentals and timing analysis Preferred Skills: • Experience with SoC FPGA platforms (e.g., Xilinx Zynq, Intel SoC FPGA) • Familiarity with AXI/AHB or similar bus protocols • Exposure to ASIC design flow, including synthesis and STA • Experience with high-speed interfaces (e.g., PCIe, Ethernet) • Knowledge of communication systems (e.g., 5G PHY/MAC concepts) What Success Looks Like: • Independently handles well-defined design blocks from RTL to FPGA validation • Produces clean, efficient, and timing-aware RTL • Effectively debugs issues across simulation and hardware • Collaborates well within a team and contributes to overall project progress • Continuously improves technical depth and delivery efficiency Additional Requirements This is a fast-paced, high-impact environment - flexibility to occasionally work extended hours or weekends during critical periods is expected. This is a full time, exempt position, based out of our Saratoga office. The target base pay for this position is $120,000 - $220,000 annually. The total compensation packaged will be determined by various factors such as your relevant job-related knowledge, skills, and experience. We are redefining how satellites are designed, manufactured and used—so we’re looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities. If that’s your experience – then we’ll be immediately wow-ed. E-Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role. Why E-Space is right for you: As a member of our team, you will play a crucial role in driving our success. Our team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet. This means that there will be times when extra hours, including nights and weekends, may be needed to meet critical deadlines and mission goals. In return, we offer a dynamic work environment with opportunities for professional growth and development and the chance to make a meaningful impact in a high-growth industry. We want you to make the most of your journey at E-Space. That’s why we support and invest in the physical, emotional and financial well-being of our team members and their families. Some of what you can expect when working at E-Space: • An opportunity to really make a difference • Sustainability at our core • Fair and honest workplace • Innovative thinking is encouraged • Competitive salaries • Continuous learning and development • Health and wellness care options • Financial solutions for the future • Optional legal services (US only) • Paid holidays • Paid time off

Requirements

Must-haves

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place!
Design and implement RTL using SystemVerilog with consideration for timing, power, and area
Perform FPGA prototyping, validation, and hardware bring-up for digital designs
Develop and execute simulation and debugging strategies at block and subsystem levels
Contribute to SoC-level integration, including interfacing with processors, memory, and peripherals
Analyze and resolve timing issues, including setup/hold violations and basic clock domain crossing concerns
Collaborate with verification, ASIC, and software teams to ensure functional correctness and performance
Participate in design reviews and contribute to improving design quality and best practices
Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field
Strong experience writing synthesizable SystemVerilog/Verilog
Proven experience with FPGA development flows, including synthesis, implementation, and validation
Solid understanding of digital design fundamentals and timing analysis
Independently handles well-defined design blocks from RTL to FPGA validation
Produces clean, efficient, and timing-aware RTL
Effectively debugs issues across simulation and hardware
Collaborates well within a team and contributes to overall project progress
Continuously improves technical depth and delivery efficiency
Additional Requirements
This is a fast-paced, high-impact environment - flexibility to occasionally work extended hours or weekends during critical periods is expected.

Nice-to-haves

Experience with SoC FPGA platforms (e.g., Xilinx Zynq, Intel SoC FPGA)
Familiarity with AXI/AHB or similar bus protocols
Exposure to ASIC design flow, including synthesis and STA
Experience with high-speed interfaces (e.g., PCIe, Ethernet)
Knowledge of communication systems (e.g., 5G PHY/MAC concepts)

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: lever
Effort: quick

Benefits

Benefits detected in the listing.

Paid Time Off

Wellness