Job description

ABOUT NEUROPHOS The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach. Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference. We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A neurophos.com led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. Join us and shape the future of computing! POSITION OVERVIEW You'll be the SoC Lead who owns integration of the full chip, or a major module or subsystem, for a system built around a bandwidth problem most digital teams never face. This is a breadth role: you'll make and defend decisions across DFT, power, timing, and interconnect architecture, with the tapeout scars to know where those decisions bite later. You'll work closely with System Architects, RTL, physical design, and verification leads to close on system-level tradeoffs, and you'll help us scale the design org by hiring and mentoring the specialists under you. LOCATION Austin, TX or San Jose, CA. Full-time onsite position. KEY RESPONSIBILITIES - Lead integration of the full chip, or a major module/subsystem, including ownership of top-level integration flows. - Make and own cross-domain technical decisions spanning system functionality, DFT, power, timing, and interconnect/data-fabric architecture. - Partner across microarchitecture, RTL, physical design, verification, and DFT to resolve system-level tradeoffs. - Go deep on any domain when needed, staying hands-on with the flow at every level. - Help scale the design org: hire, mentor, and grow engineers across specialty domains (subsystem roles are open now and will continue to open). - Represent chip-level architecture in the context of advanced-node, high-speed, high-bandwidth, low-power, physically large designs. QUALIFICATIONS - Principal-level (or equivalent) technical leadership experience at a semiconductor or systems company, with multiple full-chip tapeouts. - Demonstrated breadth across domains: for example, you've closed timing on a block and argued interconnect architecture in the same design cycle. - Deep experience in at least one of: CPU design, or high-speed interconnect / data-fabric design. Interconnect and data-fabric work is especially central to what we're building. - Experience with advanced process nodes, high-bandwidth I/O, and large, physically big subsystem or full-chip designs. PREFERRED SKILLS - Cadence toolchain experience. - Comfortable being evaluated as either an individual-contributor technical leader or a people manager; we're open to either path for the right person. - Familiarity with AI/ML accelerator or large-scale compute workloads, though not required. - Familiarity with AI-assisted EDA flows in the Cadence toolchain (e.g., Cerebrus) for synthesis, timing closure, or verification. WHAT WE OFFER This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on game-changing technology at the intersection of photonics and AI as part of a collaborative, brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world. BENEFITS Join a team that invests in your future and your well-being. At Neurophos, we offer: - 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions. - Unlimited PTO. No rigid vacation banks, just a focus on delivery. - 401(k) matching and stock option opportunities to ensure our success is your success. - Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance. - Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.

Requirements

Must-haves

Austin, TX or San Jose, CA. Full-time onsite position.
Lead integration of the full chip, or a major module/subsystem, including ownership of top-level integration flows.
Make and own cross-domain technical decisions spanning system functionality, DFT, power, timing, and interconnect/data-fabric architecture.
Partner across microarchitecture, RTL, physical design, verification, and DFT to resolve system-level tradeoffs.
Go deep on any domain when needed, staying hands-on with the flow at every level.
Help scale the design org: hire, mentor, and grow engineers across specialty domains (subsystem roles are open now and will continue to open).
Represent chip-level architecture in the context of advanced-node, high-speed, high-bandwidth, low-power, physically large designs.
Principal-level (or equivalent) technical leadership experience at a semiconductor or systems company, with multiple full-chip tapeouts.
Demonstrated breadth across domains: for example, you've closed timing on a block and argued interconnect architecture in the same design cycle.
Deep experience in at least one of: CPU design, or high-speed interconnect / data-fabric design. Interconnect and data-fabric work is especially central to what we're building.
Experience with advanced process nodes, high-bandwidth I/O, and large, physically big subsystem or full-chip designs.
Familiarity with AI/ML accelerator or large-scale compute workloads, though not required.

Nice-to-haves

Cadence toolchain experience.
Comfortable being evaluated as either an individual-contributor technical leader or a people manager; we're open to either path for the right person.
Familiarity with AI-assisted EDA flows in the Cadence toolchain (e.g., Cerebrus) for synthesis, timing closure, or verification.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aigoml

Platform: ashby
Effort: quick

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)

Pto