Job description

Job Details: Job Description: About the Role Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Mid-level Physical Design Engineer CPU, you will contribute to delivering high-performance, power-efficient silicon using advanced process technologies. In this role, you will take on increasing ownership within the RTL-to-GDS flow, working on block-level implementation while collaborating closely with cross-functional teams. This position offers strong growth opportunities as you build depth in physical design and SoC development. What You’ll Do Key responsibilities will include but not limited to: Execute physical design implementation for CPU core blocks or subsystems Perform synthesis, floor planning, place and route (PnR), and design closure activities Conduct static timing analysis (STA), power analysis, and physical verification Identify and debug timing, power, and design rule violations Contribute to achieving timing, power, and area (PPA) targets Develop and maintain scripts for design automation (e.g., TCL, Python) Collaborate with RTL design, verification, clocking, and full-chip teams Support improvements to design flows, methodologies, and best practices Document technical work and share knowledge within the team Behavioral traits that we are looking for: Strong analytical and problem-solving skills Takes ownership of assigned tasks and delivers with accountability Works effectively in collaborative, cross-functional environments Communicates technical information clearly and concisely Shows adaptability in a fast-paced, evolving engineering environment Demonstrates continuous learning and skill development Why Join Us Work on cutting-edge CPU core designs that power client, server, IoT, and AI platforms used worldwide Be part of a team driving innovation at advanced semiconductor process nodes Contribute across the full RTL-to-GDS flow, gaining exposure to complex, high-impact silicon design Collaborate with experienced engineers across architecture, design, and full-chip integration Grow your technical expertise through challenging problems, modern tools, and continuous learning opportunities Join a culture that values inclusion, collaboration, and diverse perspectives while delivering industry-leading technology Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. See Intel Benefits for more details. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Note: For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information Minimum Qualifications and Experience : Bachelors in Computer / Electrical Engineering or related field with 5 years of relevant work experience. Or a Masters in the same field with 3 years of relevant work experience. Your experience described above must be in the following: Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure PV convergence (including static timing and power analysis) Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby) Experience with one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP Preferred Qualifications and Experience : Industry experience/exposure with CPU Micro-Architecture Physical design best known practices concerning floor-planning, routing techniques, clock distribution Static Timing Analysis, Noise analysis, and reliability verification techniques RTL to GDS methodologies and formal equivalence Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus) Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Requirements

Must-haves

Job Description: About the Role
What You’ll Do
Key responsibilities will include but not limited to:
Execute physical design implementation for CPU core blocks or subsystems
Perform synthesis, floor planning, place and route (PnR), and design closure activities
Conduct static timing analysis (STA), power analysis, and physical verification
Identify and debug timing, power, and design rule violations
Contribute to achieving timing, power, and area (PPA) targets
Develop and maintain scripts for design automation (e.g., TCL, Python)
Collaborate with RTL design, verification, clocking, and full-chip teams
Support improvements to design flows, methodologies, and best practices
Document technical work and share knowledge within the team
Strong analytical and problem-solving skills
Takes ownership of assigned tasks and delivers with accountability
Works effectively in collaborative, cross-functional environments
Communicates technical information clearly and concisely
Shows adaptability in a fast-paced, evolving engineering environment
Demonstrates continuous learning and skill development
For information on Intel’s immigration sponsorship guidelines, please see
Intel U.S. Immigration Sponsorship Information
Bachelors in Computer / Electrical Engineering or related field with 5 years of relevant work experience. Or a Masters in the same field with 3 years of relevant work experience.
Your experience described above must be in the following:
Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
PV convergence (including static timing and power analysis)

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aipython

Platform: workday
Effort: long