Job description

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: We are seeking a Digital Mixed-Signal Lead with a strong digital design and architecture background to lead the development of digital control infrastructures for advanced clocking sub-systems ( PLLs, FLLs, and DLLs ). Core Responsibilities Architecture & RTL: Own the architectural definition, RTL implementation, and system-level integration of the digital logic driving clocking IPs. Logic Design: Design complex digital control loops, state machines for adaptive calibration, DVFS (dynamic voltage/frequency scaling) controllers, and fractional-N delta-sigma modulators. Analog Interface: Serve as the primary bridge to Analog Circuit Designers. Translate analog specifications into robust digital architectures and define clean boundaries at the analog-digital interface. Verification Partnership: Partner with Verification Teams to drive Mixed-Signal Verification (MSV) and Real Number Modeling (RNM) strategies for high-coverage loop simulations. Physical Design Collaboration: Work with Physical Design Teams to co-optimize floorplanning and protect sensitive analog nodes from digital switching noise. Sign-off Methodology: Enforce a rigorous full-chip CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) sign-off methodology for the clocking network. Candidate Requirements Education: Bachelors degree Experience: 8 years of professional digital ASIC design experience. RTL Mastery: Deep expertise in writing robust, synthesizable SystemVerilog RTL Process Nodes: Direct experience with advanced technology nodes, specifically N5, N3P, and beyond . Track Record: Proven history of steering cross-functional execution from initial concept through to successful tapeout s. Compensation and Benefits The annual base salary range for this position is USD 121,900.00 To USD 195,000.00 As a valued member of our team, you ll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company s growth. All subject to relevant plan documents and award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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We are seeking a Digital Mixed-Signal Lead with a strong digital design and architecture background to lead the development of digital control infrastructures for advanced clocking sub-systems ( PLLs, FLLs, and DLLs ).
Architecture & RTL: Own the architectural definition, RTL implementation, and system-level integration of the digital logic driving clocking IPs.
Logic Design: Design complex digital control loops, state machines for adaptive calibration, DVFS (dynamic voltage/frequency scaling) controllers, and fractional-N delta-sigma modulators.
Analog Interface: Serve as the primary bridge to Analog Circuit Designers. Translate analog specifications into robust digital architectures and define clean boundaries at the analog-digital interface.
Verification Partnership: Partner with Verification Teams to drive Mixed-Signal Verification (MSV) and Real Number Modeling (RNM) strategies for high-coverage loop simulations.
Physical Design Collaboration: Work with Physical Design Teams to co-optimize floorplanning and protect sensitive analog nodes from digital switching noise.
Sign-off Methodology: Enforce a rigorous full-chip CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) sign-off methodology for the clocking network.
Candidate Requirements
Education: Bachelors degree
Experience: 8 years of professional digital ASIC design experience.
RTL Mastery: Deep expertise in writing robust, synthesizable SystemVerilog RTL
Process Nodes: Direct experience with advanced technology nodes, specifically N5, N3P, and beyond .
Track Record: Proven history of steering cross-functional execution from initial concept through to successful tapeout s.

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Platform: workday
Effort: long

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Dental

Vision

401(K)