Job description

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Silicon Manufacturing and Product Engineering team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal Test Engineer to join the team. #SCHIE #CSME Responsibilities The candidate for this position will be expected and able to complete the following responsibilities: • Responsible for product and engineering activities supporting new product development and manufacturing, with primary focus on scan (structural) test. • Contribute to silicon bring-up, validation, and manufacturing readiness while working closely with cross-functional partners. • Support semiconductor IC development across fabrication, manufacturing test, and packaging phases. • Contribute to ATE test program development, including scan pattern integration, test method implementation, bring-up, silicon characterization, debug, and yield analysis for logic defects. • Execute defined test plans and methodologies while identifying issues and escalating risks with clear technical data. • Apply working knowledge of Design-for-Test (DFT), including scan architecture, ATPG, fault models, silicon fabrication processes, product qualification and reliability, and basic transistor theory. • Collaborate with design, DFT, product, and manufacturing teams to support scan test readiness, coverage closure, and issue resolution. • Gain exposure to product domains such as high-performance computing, AI, GPUs, and telecom, as applicable to assigned projects. • Apply industry-standard DFT features, including scan (SAF/TDF), JTAG, boundary scan, and at-speed testing. • Support scan test content generation, including ATPG pattern validation, pattern bring-up, and post-silicon debug activities. • Understand scan fault models (e.g., stuck-at and transition faults), coverage targets, and defect screening methodologies. • Utilize scan diagnosis tools to perform failure analysis, identify defect locations, and support yield improvement activities. • Work with DFT teams to support simulation, emulation, and pattern verification for scan test validation. Qualifications Required Qualifications: • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. Screening Requirements • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Preferred Qualifications: • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience. 1+ year(s) experience working on or leading projects from beginning-to-end. • 5+ years of experience in integrated circuit development, including pre-silicon, first silicon bring-up, or new product introduction. • 5+ years of experience in product and test engineering, with hands-on exposure to ATE test program development, bring-up, and debug for scan. • Experience working on complex SoCs or chips, including exposure to high-performance, AI, or advanced-node designs. • Clear written and verbal communication skills with the ability to present technical data effectively. • Experience collaborating with cross-functional teams in a structured development environment. • Working knowledge of probability, statistics, and basic DOE concepts. • Familiarity with DFT and DFM techniques, with emphasis on scan/structural test methodologies. • Experience with scan/ATPG methodologies, including pattern generation, validation, and test flows. • Understanding silicon bring-up, debug, and characterization on ATE platforms (e.g., Advantest 93K) for scan test content. • Exposure to mixed-signal IP test development and its interaction with structural test is a plus. • Basic device physics background. • Demonstrated adaptability, curiosity, and constructive problem-solving approach. • Strong Growth Mindset with a desire to learn and expand technical depth. • Fundamentals of computer architecture. • Good unit and integration testing skills. • Proficiency with Linux-based environments. • Experience debugging and optimizing test programs, ATPG patterns, or validation flows. • Customer-focused mindset with attention to quality, coverage, and execution. • Demonstrated ability to deliver results on assigned tasks with guidance. • Sound technical judgment in scoping and resolving well-defined problems. Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: careers.microsoft.com This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Requirements

Must-haves

We are looking for a Principal Test Engineer to join the team.
The candidate for this position will be expected and able to complete the following responsibilities:
Responsible for product and engineering activities supporting new product development and manufacturing, with primary focus on scan (structural) test.
Contribute to silicon bring-up, validation, and manufacturing readiness while working closely with cross-functional partners.
Support semiconductor IC development across fabrication, manufacturing test, and packaging phases.
Contribute to ATE test program development, including scan pattern integration, test method implementation, bring-up, silicon characterization, debug, and yield analysis for logic defects.
Execute defined test plans and methodologies while identifying issues and escalating risks with clear technical data.
Apply working knowledge of Design-for-Test (DFT), including scan architecture, ATPG, fault models, silicon fabrication processes, product qualification and reliability, and basic transistor theory.
Collaborate with design, DFT, product, and manufacturing teams to support scan test readiness, coverage closure, and issue resolution.
Gain exposure to product domains such as high-performance computing, AI, GPUs, and telecom, as applicable to assigned projects.
Apply industry-standard DFT features, including scan (SAF/TDF), JTAG, boundary scan, and at-speed testing.
Support scan test content generation, including ATPG pattern validation, pattern bring-up, and post-silicon debug activities.

Nice-to-haves

Experience working on complex SoCs or chips, including exposure to high-performance, AI, or advanced-node designs.
Clear written and verbal communication skills with the ability to present technical data effectively.
Experience collaborating with cross-functional teams in a structured development environment.
Working knowledge of probability, statistics, and basic DOE concepts.
Familiarity with DFT and DFM techniques, with emphasis on scan/structural test methodologies.
Experience with scan/ATPG methodologies, including pattern generation, validation, and test flows.
Understanding silicon bring-up, debug, and characterization on ATE platforms (e.g., Advantest 93K) for scan test content.
Exposure to mixed-signal IP test development and its interaction with structural test is a plus.
Basic device physics background.
Demonstrated adaptability, curiosity, and constructive problem-solving approach.
Strong Growth Mindset with a desire to learn and expand technical depth.
Fundamentals of computer architecture.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

azureai

Platform: eightfold
Effort: medium

Benefits

Benefits detected in the listing.

Vision