Job description

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As an ASIC Formal Verification Engineer, you will contribute formal verification expertise to verify the digital designs, with a specific focus on TPU architecture and its integration within AI/ML- driven systems. You will be part of a team developing ASICs used to accelerate computation in data centers. You will have responsibilities in areas such as project definition, formal verification, and silicon bringup. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits Learn more about benefits at Google . • Plan the formal verification strategy, create the properties and constraints for the digital design blocks. • Utilize formal property verification tools combined with formal verification closure techniques to verify properties. • Resolve difficult to verify properties. • Contribute improvements to methodologies to enhance formal verification results. • Architect and implement reusable formal verification components. • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. • 4 years of experience with formal and design verification. • Experience with SystemVerilog or Verilog. • Experience working with one or more formal verification tools (e.g., Jasper, VC Formal, Questa Formal, 360-DV). Minimum qualifications: • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. • 4 years of experience with formal and design verification. • Experience with SystemVerilog or Verilog. • Experience working with one or more formal verification tools (e.g., Jasper, VC Formal, Questa Formal, 360-DV). Preferred qualifications: • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science. • 6 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based Integrated Circuits (ICs) and chips. • Experience with scripting languages. • Excellent communication and collaboration skills.

Requirements

Must-haves

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
Learn more about benefits at Google .
Plan the formal verification strategy, create the properties and constraints for the digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
Resolve difficult to verify properties.
Contribute improvements to methodologies to enhance formal verification results.
Architect and implement reusable formal verification components.
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with formal and design verification.
Experience with SystemVerilog or Verilog.
Experience working with one or more formal verification tools (e.g., Jasper, VC Formal, Questa Formal, 360-DV).
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with formal and design verification.
Experience with SystemVerilog or Verilog.
Experience working with one or more formal verification tools (e.g., Jasper, VC Formal, Questa Formal, 360-DV).
6 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based Integrated Circuits (ICs) and chips.

Nice-to-haves

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
Experience with scripting languages.
Excellent communication and collaboration skills.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aiml

Platform: google
Effort: medium