ASIC Design Engineer – Fabric/Interconnect

• -Design & Integration of coherent and non-coherent fabrics into a subsystem or SoC with good understanding of on-chip interconnect architectures (NoC topologies, crossbars, arbitration).
• Own all aspects of RTL development design, templating, scripting and RTL generation.
• Work and collaborate with other designers in the group to deliver results.
• Integrate common/shared IP blocks to design and optimize memories/hard macros required for the block.
• Work with front-end synthesis/STA teams to ensure timing for the block is met.
• Work with power/performance and functional verification team to ensure high quality of the block.
• Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process
• Minimum of BS + 0 years relevant industry experience.
• Knowledge of cache coherency protocols (MESI, MOESI, directory-based coherence) and memory hierarchy.
• A consistent track record of delivering large, sophisticated designs in high volume production for low power applications
• Solid working experience with synthesis, power, performance and verification teams to develop and deliver high quality RTL design on time
• Strong interpersonal skills, as the candidate will work with diverse groups within the company
• Self-starter, highly motivated, highly organized, and schedule driven
• Familiarity with all front-end tools including lint, CDC, synthesis

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