Job description

About Unconventional Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented demand for computation—a demand that is now fundamentally limited by energy, not just in the datacenter, but at a global scale. At Unconventional , our mission is to solve this. We are rethinking computing from the ground up to build a new foundation for AI that is 1000x more efficient . We're doing this by exploiting the rich physics of semiconductors, mapping neural networks directly to the device physics rather than relying on layers of inefficient abstraction. The Role As a Member of Technical Staff, Physical Design Engineer , you will be a foundational member of our multi-disciplinary R&D team. We are looking for individuals who thrive at the intersection of architecture and silicon, turning novel AI concepts into high-performance, energy-efficient hardware. You will be responsible for the "back-end" realization of our novel computing platform, taking complex digital logic from RTL to GDSII. Responsibilities Full RTL-to-GDSII Ownership: Lead the physical implementation of complex, high-performance blocks and top-level SoC integration. This includes floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and physical verification. PPA Optimization: Drive aggressive Power, Performance, and Area (PPA) targets. You will work closely with architects to influence the micro-architecture for better physical routability and timing closure. Sign-off & Verification: Own the final sign-off process, including Static Timing Analysis (STA), IR drop analysis (static and dynamic), Electromigration (EM), and Physical Verification (DRC/LVS/ERC). Methodology Development: Contribute to the development and automation of our physical design flow. Set best practices for synthesis, formal verification (LEC), and parasitic extraction to ensure first-pass silicon success. Cross-Functional Collaboration: Work at the interface of digital and analog design, facilitating the integration of custom analog mixed-signal blocks into the digital fabric. Partner Engagement: Work to evaluate potential partners that offer AI tools that could greatly improve chip design efficiency Minimum Qualifications Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field. Experience: 10+ years of industry experience in digital physical design, with a track record of successful tapeouts on modern process nodes ( 7nm, 5nm, or newer preferred ). Technical Expertise: Expertise in Static Timing Analysis (STA) and timing closure for high-frequency, complex designs. Deep understanding of physical design challenges in advanced nodes (multi-patterning, finFET effects, low-voltage operation). Proficiency in power integrity analysis and noise coupling mitigation. Design Flow Proficiency: Expert-level mastery of standard EDA tool suites (e.g., Synopsys Fusion Compiler/IC Compiler II or Cadence Innovus). Strong scripting skills in Tcl, Python, or Perl to automate design flows and data analysis. Communication: Excellent written and verbal communication skills, with experience managing deliverables from external vendors or design houses. Preferred Qualifications (Nice to Have) Custom AI Hardware: Experience with physical design for Machine Learning accelerators or large-scale systolic arrays. Mixed-Signal Integration: Experience with top-level integration of large, custom analog macros and complex power-sequencing requirements. Low Power Design: Hands-on experience with multi-voltage domains, UPF/CPF flows, and advanced power-gating techniques. AI Tools: Familiarity with state of the art AI tools to accelerate chip design. Why Join Us? The Mission: Redefine computing for the next 50 years by solving the fundamental energy limitation of AI at a global scale. The Impact: Shape the company's future as a foundational team member. Enjoy massive ownership and an outsized opportunity to drive change. The Challenge: Dive into deeply complex, intellectually stimulating, and unsolved problems at the cutting edge of multiple, converging fields. The Perks: A comprehensive package including best-in-class health benefits, 401k matching, truly unlimited PTO, and complimentary meals in our Mountain View office.

Requirements

Must-haves

You will be responsible for the "back-end" realization of our novel computing platform, taking complex digital logic from RTL to GDSII.
PPA Optimization: Drive aggressive Power, Performance, and Area (PPA) targets. You will work closely with architects to influence the micro-architecture for better physical routability and timing closure.
Sign-off & Verification: Own the final sign-off process, including Static Timing Analysis (STA), IR drop analysis (static and dynamic), Electromigration (EM), and Physical Verification (DRC/LVS/ERC).
Cross-Functional Collaboration: Work at the interface of digital and analog design, facilitating the integration of custom analog mixed-signal blocks into the digital fabric.
Partner Engagement: Work to evaluate potential partners that offer AI tools that could greatly improve chip design efficiency
Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
Expertise in Static Timing Analysis (STA) and timing closure for high-frequency, complex designs.
Deep understanding of physical design challenges in advanced nodes (multi-patterning, finFET effects, low-voltage operation).
Proficiency in power integrity analysis and noise coupling mitigation.
Expert-level mastery of standard EDA tool suites (e.g., Synopsys Fusion Compiler/IC Compiler II or Cadence Innovus).
Strong scripting skills in Tcl, Python, or Perl to automate design flows and data analysis.
Communication: Excellent written and verbal communication skills, with experience managing deliverables from external vendors or design houses.
Custom AI Hardware: Experience with physical design for Machine Learning accelerators or large-scale systolic arrays.
Mixed-Signal Integration: Experience with top-level integration of large, custom analog macros and complex power-sequencing requirements.
Low Power Design: Hands-on experience with multi-voltage domains, UPF/CPF flows, and advanced power-gating techniques.
AI Tools: Familiarity with state of the art AI tools to accelerate chip design.
Why Join Us?
The Mission: Redefine computing for the next 50 years by solving the fundamental energy limitation of AI at a global scale.
The Impact: Shape the company's future as a foundational team member. Enjoy massive ownership and an outsized opportunity to drive change.
The Challenge: Dive into deeply complex, intellectually stimulating, and unsolved problems at the cutting edge of multiple, converging fields.

Nice-to-haves

Experience: 10+ years of industry experience in digital physical design, with a track record of successful tapeouts on modern process nodes ( 7nm, 5nm, or newer preferred ).
Preferred Qualifications (Nice to Have)

Application prep

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Keywords to mirror

aipythonmachine learning

Platform: greenhouse
Effort: quick

Benefits

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401k

Pto