Job description

Principal ASIC Design Engineer This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: Job Family Definition: Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits. Analyzes designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions. May direct support personnel in the preparation of detailed design, design testing and prototype fabrication. Management Level Definition: Contributions have visible technical impact on a product or major subcomponent. Applies in-depth professional knowledge and innovative ideas to solve complex problems. Visible contributions improve time-to-market, achieve cost reductions, or satisfy current and future unmet customer needs. Recognized internal authority on key technology area applying innovative principles and ideas. Provides technical leadership for significant project/program work. Leads or participates in cross-functional initiatives and contributes to mentorship and knowledge sharing across the organization. Responsibilities: Architect complex modules and subsystems used in high performance networking chips. Write detailed functional as well as the micro-architecture specification for your module with that meet the power/area/performance targets. Implement the design using Verilog or System Verilog Write functional coverage/SVA to help verification catch corner case bugs. Make sure your module meets the power targets by using state-of-the-art power reduction techniques during architecture and implementation phases. Work with Physical design team for timing closure. Fix timing in RTL to meet the frequency target. Collaborate with the Verification team to make sure your block is fully validated. Show leadership and provide guidance to new college-grad/junior engineers and interns. Recommended skills Bachelor’s degree in Electrical Engineering required (Master’s strongly desired) with 15 years of relevant experience. Strong analytical/ problem solving skills. Demonstrated skills in leading and implementing high performance subsystems from specification to final netlist. Knowledge of Computer Architecture/networking protocols through prior work is strongly desired. Strong coding skills in Verilog/System Verilog through previous work experience are necessary. Knowledge of synthesis/lint and other tools used in typical ASIC development process is highly desired. Excellent written and verbal communications skills is necessary. Knowledge of Perl/Python is strongly desired. What We Can Offer You: Health & Wellbeing We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing. Personal & Professional Development We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division. Unconditional Inclusion We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. Let s Stay Connected: Follow HPECareers on Instagram to see the latest on people, culture and tech at HPE. #unitedstates Job: Engineering Job Level: TCP_05 "The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level. – United States of America: Annual Salary USD 174,000 - 352,500 in California The listed salary range reflects base salary. Variable incentives may also be offered." Information about employee benefits offered in the US can be found at myhperewards.com HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity . Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities. HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories. Recruitment Fraud Alert We have become aware of an increase in fraudulent recruitment activities in which individuals impersonate our company or authorized recruitment agencies to offer fake employment opportunities. These scams may occur through false websites, emails, social media, or chat-based applications and often aim to obtain personal information or money. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We also never request personal information such as back account details, Social Security numbers, or national IDs via social media or chat applications. All legitimate job opportunities will come through official company channels, and candidates are responsible for verifying the credentials of any third party claiming to represent the company. Any reliance on fraudulent communication is at the individual’s own risk, and HPE disclaims legal liability for any resulting damages. If you suspect recruitment fraud, do not share personal information or make any payments and report the incident to your local authorities immediately.

Requirements

Must-haves

Principal ASIC Design Engineer
Architect complex modules and subsystems used in high performance networking chips.
Write detailed functional as well as the micro-architecture specification for your module with that meet the power/area/performance targets.
Implement the design using Verilog or System Verilog
Write functional coverage/SVA to help verification catch corner case bugs.
Make sure your module meets the power targets by using state-of-the-art power reduction techniques during architecture and implementation phases.
Work with Physical design team for timing closure. Fix timing in RTL to meet the frequency target.
Collaborate with the Verification team to make sure your block is fully validated.
Show leadership and provide guidance to new college-grad/junior engineers and interns.
Recommended skills
Bachelor’s degree in Electrical Engineering required (Master’s strongly desired) with 15 years of relevant experience.
Strong analytical/ problem solving skills.
Demonstrated skills in leading and implementing high performance subsystems from specification to final netlist.
Knowledge of Computer Architecture/networking protocols through prior work is strongly desired.
Strong coding skills in Verilog/System Verilog through previous work experience are necessary.
Knowledge of synthesis/lint and other tools used in typical ASIC development process is highly desired.
Excellent written and verbal communications skills is necessary.
Knowledge of Perl/Python is strongly desired.
Health & Wellbeing
We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional Development
Unconditional Inclusion
Follow HPECareers on Instagram to see the latest on people, culture and tech at HPE.
#unitedstates

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

Vision

Professional Development