Job description

As an ASIC Design Engineer in the Pixel IP design team, you will work closely with architecture, design, and verification teams to build high performance and low power pixel processing engines. Apply your knowledge of computer architecture and digital design to create digital signal processing pipelines for capturing, improving, compressing, decompressing, and displaying digital still images and video. In this front-end design role, your tasks will include: • Perform digital hardware design by writing high-quality RTL, with embedded assertions and cover points. • Writing detailed micro-architectural specifications. • Collaborating with cross-functional teams to explore solutions that maximize performance while minimizing power and area. • Synthesizing your design and optimize for power, timing, and area. • Working closely with design verification and formal verification teams to debug and verify functionality and performance. Bachelors Degree in EE/CE. Knowledge of front-end ASIC RTL digital logic design using Verilog or System Verilog. Strong problems-solving skills using finite state machines, pipelining, parallelism, and similar computer-architecture fundamentals. Good collaboration skills with excellent written and verbal communication skills. Prefer familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB). Knowledge of front-end implementation tasks such as synthesis and timing/area/power analysis. Prefer familiarity with relevant scripting languages (Python, Perl, TCL). Familiarity with High-Level Synthesis and hardware design using SystemC/C++ languages is a plus. Background in digital signal processing concepts is a plus.

Requirements

Must-haves

In this front-end design role, your tasks will include:
Perform digital hardware design by writing high-quality RTL, with embedded assertions and cover points.
Writing detailed micro-architectural specifications.
Collaborating with cross-functional teams to explore solutions that maximize performance while minimizing power and area.
Synthesizing your design and optimize for power, timing, and area.
Working closely with design verification and formal verification teams to debug and verify functionality and performance.
Bachelors Degree in EE/CE.
Knowledge of front-end ASIC RTL digital logic design using Verilog or System Verilog.
Strong problems-solving skills using finite state machines, pipelining, parallelism, and similar computer-architecture fundamentals.
Good collaboration skills with excellent written and verbal communication skills.
Prefer familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB).
Knowledge of front-end implementation tasks such as synthesis and timing/area/power analysis.
Prefer familiarity with relevant scripting languages (Python, Perl, TCL).

Nice-to-haves

Familiarity with High-Level Synthesis and hardware design using SystemC/C++ languages is a plus.
Background in digital signal processing concepts is a plus.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: apple
Effort: medium