Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . About Astera Labs Astera Labs is a global leader in purpose-built connectivity solutions for AI and cloud infrastructure. Our semiconductor-based platforms help solve signal, data, and memory connectivity bottlenecks in the world’s most demanding computing systems. Overview As an Astera Labs Synthesis & STA Engineer – High-Speed SerDes you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of high-speed analog/mixed-signal SerDes and connectivity ASICs used in the world's leading cloud service providers, server, and network OEMs. This role requires end-to-end ownership of logic synthesis and static timing analysis across the digital portions of mixed-signal SerDes PHY designs, deep technical expertise in mixed-signal integration, and close collaboration with analog, RTL, physical design, and verification teams to ensure robust timing closure at advanced nodes. Key Responsibilities Perform RTL synthesis, driving area, power, and timing optimization for digital controller and DSP blocks within high-speed SerDes PHY designs. Author, develop, and validate SDC constraints from scratch, including clock definitions, generated clocks, multi-frequency/multi-mode constraints, I/O delays, false paths, multicycle paths, and clock-domain crossing exceptions unique to SerDes architectures. Set up and manage MMMC (Multi-Mode Multi-Corner) environments to enable accurate and efficient STA across process, voltage, and temperature (PVT) corners. Drive timing closure from synthesis through sign-off , ensuring robust timing across digital blocks embedded within analog/mixed-signal SerDes IP and full-chip SoC integration. Define and manage I/O timing budgets and interface constraints between analog and digital boundaries in hierarchical mixed-signal designs. Apply advanced sign-off methodologies at TSMC 5nm/3nm and below , including OCV/AOCV/POCV and PVT effects relevant to high-speed serial link performance. Leverage ETM/ILM libraries for hierarchical timing analysis and correlation of SerDes hard-macro blocks, balancing runtime and accuracy. Provide actionable timing feedback at both block and full-chip levels , including root cause analysis, timing debug, and ECO guidance for SerDes digital logic. Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage , developing scripts and flows to improve turnaround time. Generate and validate timing ECOs , partnering with physical design, analog, and RTL teams for quick closure on high-speed data-path and clock-path issues. Partner closely with analog/mixed-signal designers, SerDes architecture, implementation, and verification teams to drive timing convergence and provide sign-off level expertise for PHY-level and chip-level integration. Collaborate on clock tree and power domain strategies for SerDes digital blocks, ensuring compatibility with PLL/CDR-generated clocks and multi-supply domains. Basic Qualifications Bachelor's in Electrical Engineering or Computer Science required; Master's preferred . ≥8 years of experience in synthesis, timing constraints development, STA, and sign-off for high-speed mixed-signal IP in Server, Storage, Networking, or SerDes applications. Strong proficiency in writing and debugging SDC constraints , with deep understanding of clock modeling, generated clocks, clock-domain crossings, and exception handling. Expertise in STA methodology and timing closure at both block and full-chip level using Synopsys PrimeTime and/or Cadence Tempus. Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows (Formality/Conformal) in advanced nodes (5nm/3nm and below) . Proficiency with Cadence and/or Synopsys physical design/STA toolchains. Strong scripting ability ( Tcl, Python, Perl ). Ability to work independently with strong prioritization and a professional, customer-focused mindset. Preferred Experience Direct experience with high-speed SerDes, Ethernet PHY (112G/224G), or PCIe/CXL PHY digital controller and DSP timing challenges. Understanding of analog/mixed-signal integration concerns, including analog-digital interface timing, PLL/DLL/CDR clock structures, and level-shifter/isolation cell constraints. Knowledge of ECO methodologies, DFT tools , and test coverage analysis for mixed-signal designs. Experience working with IP vendors for both RTL and hard-macro integration , including Liberty (.lib), LEF, and behavioral model characterization. SystemVerilog/Verilog proficiency. Familiarity with power-aware synthesis and STA (UPF/CPF flows). Experience with high-speed clocking architectures and multi-rate clock domain management typical in SerDes designs. Salary and benefits The salary range for this position is $160,000–$200,000 . Actual compensation will depend on experience, level, location, and business need. This role may also be eligible for discretionary bonuses, equity incentives, and comprehensive benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Requirements

Must-haves

Perform RTL synthesis, driving area, power, and timing optimization for digital controller and DSP blocks within high-speed SerDes PHY designs.
Set up and manage MMMC (Multi-Mode Multi-Corner) environments to enable accurate and efficient STA across process, voltage, and temperature (PVT) corners.
Drive timing closure from synthesis through sign-off , ensuring robust timing across digital blocks embedded within analog/mixed-signal SerDes IP and full-chip SoC integration.
Define and manage I/O timing budgets and interface constraints between analog and digital boundaries in hierarchical mixed-signal designs.
Apply advanced sign-off methodologies at TSMC 5nm/3nm and below , including OCV/AOCV/POCV and PVT effects relevant to high-speed serial link performance.
Leverage ETM/ILM libraries for hierarchical timing analysis and correlation of SerDes hard-macro blocks, balancing runtime and accuracy.
Provide actionable timing feedback at both block and full-chip levels , including root cause analysis, timing debug, and ECO guidance for SerDes digital logic.
Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage , developing scripts and flows to improve turnaround time.
Generate and validate timing ECOs , partnering with physical design, analog, and RTL teams for quick closure on high-speed data-path and clock-path issues.
Partner closely with analog/mixed-signal designers, SerDes architecture, implementation, and verification teams to drive timing convergence and provide sign-off level expertise for PHY-level and chip-level integration.
Collaborate on clock tree and power domain strategies for SerDes digital blocks, ensuring compatibility with PLL/CDR-generated clocks and multi-supply domains.
≥8 years of experience in synthesis, timing constraints development, STA, and sign-off for high-speed mixed-signal IP in Server, Storage, Networking, or SerDes applications.
Strong proficiency in writing and debugging SDC constraints , with deep understanding of clock modeling, generated clocks, clock-domain crossings, and exception handling.
Expertise in STA methodology and timing closure at both block and full-chip level using Synopsys PrimeTime and/or Cadence Tempus.
Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows (Formality/Conformal) in advanced nodes (5nm/3nm and below) .

Nice-to-haves

Bachelor's in Electrical Engineering or Computer Science required; Master's preferred .
Direct experience with high-speed SerDes, Ethernet PHY (112G/224G), or PCIe/CXL PHY digital controller and DSP timing challenges.
Understanding of analog/mixed-signal integration concerns, including analog-digital interface timing, PLL/DLL/CDR clock structures, and level-shifter/isolation cell constraints.
Knowledge of ECO methodologies, DFT tools , and test coverage analysis for mixed-signal designs.
Experience working with IP vendors for both RTL and hard-macro integration , including Liberty (.lib), LEF, and behavioral model characterization.
SystemVerilog/Verilog proficiency.
Familiarity with power-aware synthesis and STA (UPF/CPF flows).
Experience with high-speed clocking architectures and multi-rate clock domain management typical in SerDes designs.
Salary and benefits

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