Job description

Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing. Efficient is seeking a Physical Design Engineer - Timing Lead to join our growing team. The Timing Lead will work on timing convergence and methodology hands on for the world’s most energy-efficient, general-purpose processor . This role will be in the newly formed hardware engineering group and will focus on designing in state of the art finfet technologies. The role is cross functional and we are a integrated highly interdisciplinary team of world class engineers. This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond! Key Responsibilities Drive and develop Timing flows, methodology for state of the art finfet and multi patterning based technologies from scratch in Cadence Tempus or Synopsys Primetime. Own and drive timing convergence of IP, Subsystem and SOC blocks. Define timing margining, PVTRC corner definitions, extraction methodology , signoff timing to SYN/PNR correlation. Develop slew rate, glitch noise checks to ensure robust design quality. Develop custom timing checks as pertains to Efficients proprietary Ultra low power architecture. Work closely with RTL team, DFT and IP vendors to define and drive SDC constraints. Have an in-depth understanding of all collaterals for all hard and soft IPs used by the design. Partner with post-si products bring up team to ensure good pre-si to post-si correlation from a timing perspective. Work with 3rd party vendor resources and coordinate their work in the timing domain. Continuously work on improving flow consistency and efficiency in the context of multiple product type swim lanes. Required Qualifications Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience Proven track record of delivering IP/SS (or SoC) STA sign-off for multiple tape-outs in 12nm or below process technologies. Experience with EDA flow using Cadence/Synopsys/Mentor tools for STA/simulations (PT/Hspice) with hierarchical design and abstraction techniques Hands-on experience in timing convergence of high-frequency and low power designs. Expert knowledge of static timing analysis, defining constraints and exceptions, corners/voltage definitions and timing margining. Experience with low power implementation typical in industry and how timing convergence impacts power draw ensuring we are making optimal tradeoffs. Excellent scripting skills in TCL, shell and python. Desired Qualifications Knowledge of computer architecture Knowledge of physical design and ASIC implementation Experience in full chip sign-off budgeting Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers. Definition of design constraints for static timing analysis (synthesis, pre/post‑cts, sign‑off) and corners/voltage definitions. Experience in integrating analog or mixed-signal macro on top-level design. We offer a competitive base salary for this role, generally ranging from $180,000 to $260,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate. Why Join Efficient? Build what's next. At Efficient, you'll tackle big challenges with room to take ownership and make an impact. We back you with competitive pay, equity, a 401(k) match, company-paid benefits, paid parental leave, and flexibility—plus opportunities to grow your skills and career as we scale.

Requirements

Must-haves

Drive and develop Timing flows, methodology for state of the art finfet and multi patterning based technologies from scratch in Cadence Tempus or Synopsys Primetime.
Own and drive timing convergence of IP, Subsystem and SOC blocks.
Define timing margining, PVTRC corner definitions, extraction methodology , signoff timing to SYN/PNR correlation.
Develop slew rate, glitch noise checks to ensure robust design quality.
Develop custom timing checks as pertains to Efficients proprietary Ultra low power architecture.
Work closely with RTL team, DFT and IP vendors to define and drive SDC constraints.
Have an in-depth understanding of all collaterals for all hard and soft IPs used by the design.
Partner with post-si products bring up team to ensure good pre-si to post-si correlation from a timing perspective.
Work with 3rd party vendor resources and coordinate their work in the timing domain.
Continuously work on improving flow consistency and efficiency in the context of multiple product type swim lanes.
Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
Proven track record of delivering IP/SS (or SoC) STA sign-off for multiple tape-outs in 12nm or below process technologies.
Experience with EDA flow using Cadence/Synopsys/Mentor tools for STA/simulations (PT/Hspice) with hierarchical design and abstraction techniques
Hands-on experience in timing convergence of high-frequency and low power designs.
Expert knowledge of static timing analysis, defining constraints and exceptions, corners/voltage definitions and timing margining.
Experience with low power implementation typical in industry and how timing convergence impacts power draw ensuring we are making optimal tradeoffs.
Excellent scripting skills in TCL, shell and python.

Nice-to-haves

Knowledge of computer architecture
Knowledge of physical design and ASIC implementation
Experience in full chip sign-off budgeting
Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design
Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers.
Definition of design constraints for static timing analysis (synthesis, pre/post‑cts, sign‑off) and corners/voltage definitions.
Experience in integrating analog or mixed-signal macro on top-level design.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aipython

Platform: greenhouse
Effort: quick

Benefits

Benefits detected in the listing.

401(K)

Parental Leave