Job description

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering ( SCHIE ) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Microsoft’s Compute Silicon & Manufacturing Engineering team is instrumental in defining and elivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Senior Physical Design Engineer to join the team to support our mission as a key role with silicon design. #SCHIE #CSME Responsibilities The candidate for this position will be expected and able to complete the following responsibilities: • Drive end-to-end execution from synthesis through place-and-route for large designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification. • Responsible for clock construction and CTS. • Drive methodology exploration activities to optimize SOC blocks for clock construction and related methodology. • Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners as essential. • Responsible for RTL to GDS implementation in Physical Design domain. • Influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach. • Foster collaboration across teams to deliver the possible solutions, aligned with a One Microsoft mindset. • Demonstrate technical expertise across various domains of Physical Design. • Clear communications on project status & planning. • Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion. Qualifications Required Qualifications: • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. Other Requirements: • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Preferred Qualifications: • BS/MS in Electrical or Computer Engineering or any related degree • Min 7+ years of experience in semiconductor design. • Communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams. • Proven track record in Physical Design domain implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification. • Production silicon tape-outs experience in advanced foundry process nodes. • Experience in low power design methodology for SOC • Thorough understanding of SOC or subsystem design trade-offs across power, performance, and area (PPA). • Familiarity with various clock construction strategies for high speed designs • Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff, Formal Equivalence, and Low Power Verification. • Own complete PD execution of medium to large-size SOC block. Be fully hands-on in technical domain ownerships as individual contributor and collaborate cross-team as required. • Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues • Problem-solving and data analysis skills • Ability to communicate effectively with cross-functional teams Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: careers.microsoft.com This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Requirements

Must-haves

We are looking for a Senior Physical Design Engineer to join the team to support our mission as a key role with silicon design.
The candidate for this position will be expected and able to complete the following responsibilities:
Responsible for clock construction and CTS.
Drive methodology exploration activities to optimize SOC blocks for clock construction and related methodology.
Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners as essential.
Responsible for RTL to GDS implementation in Physical Design domain.
Influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach.
Foster collaboration across teams to deliver the possible solutions, aligned with a One Microsoft mindset.
Demonstrate technical expertise across various domains of Physical Design.
Clear communications on project status & planning.
Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.
Min 7+ years of experience in semiconductor design.
Own complete PD execution of medium to large-size SOC block. Be fully hands-on in technical domain ownerships as individual contributor and collaborate cross-team as required.

Nice-to-haves

BS/MS in Electrical or Computer Engineering or any related degree
Communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
Proven track record in Physical Design domain implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.
Production silicon tape-outs experience in advanced foundry process nodes.
Experience in low power design methodology for SOC
Thorough understanding of SOC or subsystem design trade-offs across power, performance, and area (PPA).
Familiarity with various clock construction strategies for high speed designs
Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues
Problem-solving and data analysis skills
Ability to communicate effectively with cross-functional teams
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

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