Job description

Job ID: 115400 The Electro Optical Infrared Systems (EOIS) line of business within DRS has locations in Dallas and Austin, TX, Melbourne, FL, and Cypress, CA. EOIS develops, manufactures, and supports infrared and electro-optical solutions for soldiers, ground vehicles and airborne platforms. We offer an exciting and challenging work environment, a competitive salary and benefits package, and a business culture that rewards performance. Employing the world’s brightest. Supporting the world’s bravest. Job Summary Business Unit: EOIS Location: Dallas, TX Career Functional Area: Digital Design Engineering Telework Type: Onsite Type: Hourly Intern Schedule: 12-14 week internship on 9/80 Shift: First The individual will be an intern for the Readout Integrated Circuit (ROIC) or the FPGA development teams of the EOIS division. In this role, the intern will work closely with other team members to support development of digital integrated circuits (IC) for ROIC and Focal Plane Arrays (FPA) or support FPGA development for Infrared Sensors and Systems. Strong mentorship is provided, with plenty of opportunities to learn and develop new skills. Responsibilities will be broad, not narrow, providing for a higher growth opportunity. Job Responsibilities • Support architecture tradeoff projects • Participate in RTL coding and test bench development • Contribute in IC or FPGA design flows for synthesis, place and route, timing closure, and design verification testing Qualifications • Enrolled in an Undergraduate or Master's degree in Computer Engineering, or Electrical Engineering or related field with at least at 3.0 GPA • Be available to work full-time (40 hours per week) for at least 10 weeks during Summer 2026 at the DRS Dallas facility • U.S. Citizenship status is required as this position will require the ability to access US only data systems • Windows/Linux OS • Good listener and communication skills (verbal and written) • Ambitious, dedicated, and goal-oriented Desired Skills • Understanding of digital logic and architecture concepts, techniques, and course work • Basic knowledge of HDL/HVLs (e.g. VHDL, Verilog, System Verilog, UVM) and programming/scripting languages (e.g. C++, Perl, Python, TCL) • Good lab debug skills • Ability to multi-task in an evolving engineering environment U.S. Citizenship required. This position requires an active DOD security clearance or the ability to obtain such clearance within a reasonable time after commencement of employment. Taking care of our people is a top priority at Leonardo DRS. We are proud to offer competitive salaries and comprehensive benefits, including medical, dental, and vision coverage, a company contribution to a health savings account, telemedicine, life and disability insurance, legal insurance, and a 401(k) savings plan. We champion wellness programs that focus on physical, emotional, and financial well-being. We develop our talent by offering programs and activities to support career-growth, professional development, and skill enhancement. And we understand there is more to life than work, and the importance of offering flexible work schedules with our 9/80 program, competitive vacation, health/emergency leave, paid parental leave, and community service hours. *Some employees are eligible for limited benefits only Leonardo DRS, Inc. and its subsidiaries provide equal opportunities to all employees and applicants for employment and prohibit discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, protected veteran status, or any other characteristic protected by federal, state, or local laws.

Requirements

Must-haves

Job ID: 115400
Employing the world’s brightest. Supporting the world’s bravest.
Business Unit: EOIS
Location: Dallas, TX
Career Functional Area: Digital Design Engineering
Telework Type: Onsite
Type: Hourly Intern
Schedule: 12-14 week internship on 9/80
Shift: First
Support architecture tradeoff projects
Participate in RTL coding and test bench development
Contribute in IC or FPGA design flows for synthesis, place and route, timing closure, and design verification testing
Enrolled in an Undergraduate or Master's degree in Computer Engineering, or Electrical Engineering or related field with at least at 3.0 GPA
Be available to work full-time (40 hours per week) for at least 10 weeks during Summer 2026 at the DRS Dallas facility
U.S. Citizenship status is required as this position will require the ability to access US only data systems
Windows/Linux OS
Good listener and communication skills (verbal and written)
Ambitious, dedicated, and goal-oriented
U.S. Citizenship required. This position requires an active DOD security clearance or the ability to obtain such clearance within a reasonable time after commencement of employment.

Nice-to-haves

Understanding of digital logic and architecture concepts, techniques, and course work
Basic knowledge of HDL/HVLs (e.g. VHDL, Verilog, System Verilog, UVM) and programming/scripting languages (e.g. C++, Perl, Python, TCL)
Good lab debug skills
Ability to multi-task in an evolving engineering environment
Some employees are eligible for limited benefits only

Application prep

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python

Platform: successfactors
Effort: medium

Benefits

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Dental

Vision

401(K)

Parental Leave

Wellness

Professional Development