Job description

Leidos has a new and exciting opportunity for a Principal Hardware/Software Design Engineer in our Intelligence Sector . Our talented team is at the forefront in Security Engineering, Computer Network Operations (CNO), Mission Software, Analytical Methods and Modeling, Signals Intelligence (SIGINT), and Cryptographic Key Management. At Leidos , we offer competitive benefits , including Paid Time Off, 11 paid Holidays, 401K with a 6% company match and immediate vesting, Flexible Schedules, Discounted Stock Purchase Plans, Technical Upskilling, Education and Training Support, Parental Paid Leave, and much more. Join us and make a difference in National Security! Job Summary: Our program provides our customer s Signals Analysis organization with the best possible solutions for their mission needs. We achieve this through rapid prototyping, new development, and advanced technology research. From leading-edge visualizations to analytic development, we re always pushing the boundaries to find new and better data sources and tradecraft to answer intelligence questions. With a focus on collaboration and a fast-paced environment, our prototype development program is the ideal place to grow your skills and make a real impact. Click here to learn more about how this program “Delivers Mission Success!” Seeking an experienced Principal HW/SW Design Engineer to join a small team to design, develop, construct, and test electronic hardware (FPGA) and software processing components for subsystems supporting RF communication and collection systems. This position requires expertise in FPGA development, digital signal processing implementation, and software-hardware integration to support mission critical requirements. The contractor will lead technical design efforts, implement DSP algorithms and associated technical components in FPGA hardware, integrate with existing Linux code bases, bridge FPGA to software stack connection, plus document those efforts. This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource optimization) with software development (integration code, system-level software) to deliver complete subsystem solutions. Qualified candidates are eligible for enhanced incentives including up to a $25K cash sign on bonus or a paid time off bonus. Job Responsibilities/Qualifications: Mission Focus : Candidate is expected to implement DSP and associated technical components in FPGA for code base integration. Technical Proficiency : Strong experience required for FPGA coding, Digital Signal Processing theory & application, Interfacing FPGA code with existing code bases and software; Knowledge of signal processing blocks and related DSP components, Linux OS, coding ability in C and C . Qualifications : Bachelor s degree plus 8 years of relevant experience or equivalent. Security Clearance : Candidates must possess an active TS/SCI with Polygraph to be considered for this role. Desirable Skills : Additional experience with Vivado required; experience with Epiq Solution PDK preferred. At Leidos, the opportunities are boundless. We challenge our staff with interesting assignments that allow them to thrive professionally and personally. For us, helping you grow your career is good business. We look forward to learning more about you – apply today! Careers.leidos.com CONMD If you re looking for comfort, keep scrolling. At Leidos, we outthink, outbuild, and outpace the status quo — because the mission demands it. We re not hiring followers. We re recruiting the ones who disrupt, provoke, and refuse to fail. Step 10 is ancient history. We re already at step 30 — and moving faster than anyone else dares. Original Posting: October 9, 2026 For U.S. Positions: While subject to change based on business needs, Leidos reasonably anticipates that this job requisition will remain open for at least 3 days with an anticipated close date of no earlier than 3 days after the original posting date as listed above. Pay Range: Pay Range $154,050.00 - $278,475.00 The Leidos pay range for this job level is a general guideline only and not a guarantee of compensation or salary. Additional factors considered in extending an offer include (but are not limited to) responsibilities of the job, education, experience, knowledge, skills, and abilities, as well as internal equity, alignment with market data, applicable bargaining agreement (if any), or other law.

Requirements

Must-haves

Mission Focus : Candidate is expected to implement DSP and associated technical components in FPGA for code base integration.
Qualifications : Bachelor s degree plus 8 years of relevant experience or equivalent.
Security Clearance : Candidates must possess an active TS/SCI with Polygraph to be considered for this role.
Careers.leidos.com
Original Posting: October 9, 2026

Nice-to-haves

Desirable Skills : Additional experience with Vivado required; experience with Epiq Solution PDK preferred.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

401k

Pto

Paid Time Off