Job description

As an ASIC Design/Integration Engineer, your responsibilities span various aspects of SOC design: - Write microarchitecture and design specifications - Design, implement, and debug complex logic designs - Integrate complex IPs into the SOC - Support all front-end integration activities like Lint, CDC, RDC, Synthesis, and ECO - Work with other specialists across the SOC Design, Verification, Emulation, STA, and Physical Design teams - Collaborate with software and systems teams to ensure high quality BS and a minimum of 3 years of relevant industry experience Verilog RTL logic design experience Proven experience and solid knowledge in CDC and low-power methodologies Familiarity with scripting languages like Perl, Python, or Tcl Familiarity with GenAI tools and workflows Experience writing specifications and converting them into design Experience with multiple clock domains and asynchronous interfaces Hands-on experience across the entire chip development process with proficiency in front-end tools and methodologies Experience with or knowledge of system architecture, CPU & IP integration, and power/clock management design Strong communication skills across cross-functional internal teams Familiarity with software and operating system concepts is a plus

Requirements

Must-haves

As an ASIC Design/Integration Engineer, your responsibilities span various aspects of SOC design:
Write microarchitecture and design specifications
Design, implement, and debug complex logic designs
Integrate complex IPs into the SOC
Support all front-end integration activities like Lint, CDC, RDC, Synthesis, and ECO
Work with other specialists across the SOC Design, Verification, Emulation, STA, and Physical Design teams
Collaborate with software and systems teams to ensure high quality
BS and a minimum of 3 years of relevant industry experience
Verilog RTL logic design experience
Proven experience and solid knowledge in CDC and low-power methodologies
Familiarity with scripting languages like Perl, Python, or Tcl
Familiarity with GenAI tools and workflows
Experience writing specifications and converting them into design
Experience with multiple clock domains and asynchronous interfaces
Hands-on experience across the entire chip development process with proficiency in front-end tools and methodologies
Experience with or knowledge of system architecture, CPU & IP integration, and power/clock management design
Strong communication skills across cross-functional internal teams

Nice-to-haves

Familiarity with software and operating system concepts is a plus

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: apple
Effort: medium