Job description

As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip floorplan, area optimizations, block partitioning and pin placements • Own chip level place and route (PnR), final CPU layout database construction and verification (PDV) • Develop and validate Power Grid, including routability analysis • Drive custom layout integration, block and full-chip level EM/IR, electrical verification/analysis as well as formal verification • Work with the implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with the SOC team to meet IP technical and delivery requirements • Participate in establishing CAD and physical design methodologies and flow development for chip integration and analysis • Scripting to automate tasks and improve debug efficiency Minimum BS and 10+ years of relevant industry experience Experience with scripting in Perl or TCL Knowledge of industrial standards and practices in Physical Design, including Floorplanning, Partitioning, Budgeting, Place and Route and Physical Verification Experience in developing and implementing Power Grid and Clock specifications Solid knowledge of Low Power Design, Physical Construction, Integration, EMIR (Drop/Noise), SIGEM Analysis, Formal Verification, Physical PDV, DRC/LVS Verification, and DFM Solid understanding of verification tools such as Conformal LP, LEC, RedHawk, Calibre Solid understanding of CMOS circuit design. Layout design background is a plus Working knowledge of Extraction and STA methodology and tools Working knowledge of Computer Architecture Ability to work well in a team, being an excellent problem solver, and self motivated

Requirements

Must-haves

As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development.
Full chip floorplan, area optimizations, block partitioning and pin placements
Own chip level place and route (PnR), final CPU layout database construction and verification (PDV)
Develop and validate Power Grid, including routability analysis
Drive custom layout integration, block and full-chip level EM/IR, electrical verification/analysis as well as formal verification
Work with the implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout
Work with the SOC team to meet IP technical and delivery requirements
Participate in establishing CAD and physical design methodologies and flow development for chip integration and analysis
Scripting to automate tasks and improve debug efficiency
Minimum BS and 10+ years of relevant industry experience
Experience with scripting in Perl or TCL
Knowledge of industrial standards and practices in Physical Design, including Floorplanning, Partitioning, Budgeting, Place and Route and Physical Verification
Experience in developing and implementing Power Grid and Clock specifications
Solid knowledge of Low Power Design, Physical Construction, Integration, EMIR (Drop/Noise), SIGEM Analysis, Formal Verification, Physical PDV, DRC/LVS Verification, and DFM
Solid understanding of verification tools such as Conformal LP, LEC, RedHawk, Calibre
Working knowledge of Extraction and STA methodology and tools
Working knowledge of Computer Architecture
Ability to work well in a team, being an excellent problem solver, and self motivated

Nice-to-haves

Solid understanding of CMOS circuit design. Layout design background is a plus

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: apple
Effort: medium